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From: Tom Tromey <tom@tromey.com>
To: Jim Wilson <jimw@sifive.com>
Cc: gdb-patches@sourceware.org
Subject: Re: New ARI warning Thu Aug  9 01:56:05 UTC 2018
Date: Thu, 09 Aug 2018 16:01:00 -0000	[thread overview]
Message-ID: <87bmab8r8m.fsf@tromey.com> (raw)
In-Reply-To: <20180809015605.GA57522@sourceware.org> (GDB Administrator's	message of "Thu, 9 Aug 2018 01:56:05 +0000")

>>>>> ">" == GDB Administrator <gdbadmin@sourceware.org> writes:

>> 482a483
>> gdb/riscv-tdep.h:84: code: function call in first column: Function
>> name in first column should be restricted to function implementation
>> gdb/riscv-tdep.h:84:riscv_software_single_step (struct regcache *regcache);

Here's a patch to fix a few minor formatting issues in riscv-tdep.h,
including the one pointed out by ARI.

Let me know what you think.

Tom

diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index 4d0593f1630..5e0e0e2a035 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,7 @@
+2018-08-09  Tom Tromey  <tom@tromey.com>
+
+	* riscv-tdep.h: Minor formatting fixes.
+
 2018-08-08  Simon Marchi  <simon.marchi@ericsson.com>
 
 	* target.c (str_comma_list_concat_elem): Fix typo in comment.
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index 85911169221..8358d4e00ba 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -1,4 +1,5 @@
-/* Target-dependent header for the RISC-V architecture, for GDB, the GNU Debugger.
+/* Target-dependent header for the RISC-V architecture, for GDB, the
+   GNU Debugger.
 
    Copyright (C) 2018 Free Software Foundation, Inc.
 
@@ -39,7 +40,8 @@ enum
   RISCV_LAST_FP_REGNUM = 64,	/* Last Floating Point Register */
 
   RISCV_FIRST_CSR_REGNUM = 65,  /* First CSR */
-#define DECLARE_CSR(name, num) RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
+#define DECLARE_CSR(name, num) \
+  RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
 #include "opcode/riscv-opc.h"
 #undef DECLARE_CSR
   RISCV_LAST_CSR_REGNUM = 4160,
@@ -80,7 +82,7 @@ struct gdbarch_tdep
 extern int riscv_isa_xlen (struct gdbarch *gdbarch);
 
 /* Single step based on where the current instruction will take us.  */
-extern std::vector<CORE_ADDR>
-riscv_software_single_step (struct regcache *regcache);
+extern std::vector<CORE_ADDR> riscv_software_single_step
+  (struct regcache *regcache);
 
 #endif /* RISCV_TDEP_H */


  reply	other threads:[~2018-08-09 16:01 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-09  1:56 GDB Administrator
2018-08-09 16:01 ` Tom Tromey [this message]
2018-08-09 16:45   ` Jim Wilson

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