From: Yao Qi <qiyaoltc@gmail.com>
To: Antoine Tremblay <antoine.tremblay@ericsson.com>
Cc: <gdb-patches@sourceware.org>
Subject: Re: [PATCH v6 3/7] Refactor arm_software_single_step to use regcache.
Date: Mon, 07 Dec 2015 14:32:00 -0000 [thread overview]
Message-ID: <86fuzes51n.fsf@gmail.com> (raw)
In-Reply-To: <1449254773-19019-4-git-send-email-antoine.tremblay@ericsson.com> (Antoine Tremblay's message of "Fri, 4 Dec 2015 13:46:09 -0500")
Antoine Tremblay <antoine.tremblay@ericsson.com> writes:
> +/* Calculate the offset from stack pointer of the pc register on the stack
> + in the case of a sigreturn or sigreturn_rt syscall. */
> +static int
> +arm_linux_sigreturn_next_pc_offset (unsigned long sp,
> + unsigned long sp_data,
> + unsigned long svc_number)
> +{
> + /* Offset of R0 register. */
> + int r0_offset = 0;
> + /* Offset of PC register. */
> + int pc_offset = 0;
> +
> + gdb_assert (svc_number == 119 || svc_number == 173);
> +
> + /* sigreturn. */
> + if (svc_number == 119)
Can we get rid of these magic numbers?
> + {
> + if (sp_data == ARM_NEW_SIGFRAME_MAGIC)
> + r0_offset = ARM_UCONTEXT_SIGCONTEXT + ARM_SIGCONTEXT_R0;
> + else
> + r0_offset = ARM_SIGCONTEXT_R0;
> + }
> + /* rt_sigreturn. */
> + else if (svc_number == 173)
> + {
> + if (sp_data == sp + ARM_OLD_RT_SIGFRAME_SIGINFO)
> + r0_offset = ARM_OLD_RT_SIGFRAME_UCONTEXT + ARM_UCONTEXT_SIGCONTEXT
> + + ARM_SIGCONTEXT_R0;
> + else
> + r0_offset = ARM_NEW_RT_SIGFRAME_UCONTEXT + ARM_UCONTEXT_SIGCONTEXT
> + + ARM_SIGCONTEXT_R0;
> + }
> +
> + pc_offset = r0_offset + 4 * 15;
> +
> + return pc_offset;
> +}
> +
> +
> /* At a ptrace syscall-stop, return the syscall number. This either
> comes from the SWI instruction (OABI) or from r7 (EABI).
>
> @@ -862,21 +924,21 @@ arm_linux_get_syscall_number (struct gdbarch *gdbarch,
> instruction to be executed. */
>
> static CORE_ADDR
> -arm_linux_syscall_next_pc (struct frame_info *frame)
> +arm_linux_syscall_next_pc (struct regcache *regcache)
> {
> - CORE_ADDR pc = get_frame_pc (frame);
> - CORE_ADDR return_addr = 0;
> - int is_thumb = arm_frame_is_thumb (frame);
> + CORE_ADDR pc = regcache_read_pc (regcache);
> + CORE_ADDR next_pc = 0;
> + int is_thumb = arm_is_thumb (regcache);
Nit: looks you rename return_addr to next_pc. If you don't that, the patch
can be shorter. On the other hand, return_addr sounds a good variable
name to me, which means the address after syscall returns.
--
Yao (齐尧)
next prev parent reply other threads:[~2015-12-07 14:32 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-04 18:46 [PATCH v6 0/6] Support software single step and conditional breakpoints on ARM in GDBServer Antoine Tremblay
2015-12-04 18:46 ` [PATCH v6 2/7] Share some ARM target dependent code from GDB with GDBServer Antoine Tremblay
2015-12-04 18:46 ` [PATCH v6 4/7] Share regcache function regcache_raw_read_unsigned Antoine Tremblay
2015-12-07 14:40 ` Yao Qi
2015-12-07 14:49 ` Antoine Tremblay
2015-12-04 18:46 ` [PATCH v6 3/7] Refactor arm_software_single_step to use regcache Antoine Tremblay
2015-12-07 14:32 ` Yao Qi [this message]
2015-12-07 14:48 ` Antoine Tremblay
2015-12-07 15:21 ` Yao Qi
2015-12-07 17:37 ` Antoine Tremblay
2015-12-07 14:51 ` Yao Qi
2015-12-07 14:51 ` Antoine Tremblay
2015-12-04 18:46 ` [PATCH v6 1/7] Replace breakpoint_reinsert_addr by get_next_pcs operation in GDBServer Antoine Tremblay
2015-12-04 18:47 ` [PATCH v6 5/7] Support software single step on ARM " Antoine Tremblay
2015-12-07 15:18 ` Yao Qi
2015-12-07 15:58 ` Antoine Tremblay
2015-12-04 18:47 ` [PATCH v6 6/7] Enable software single stepping for while-stepping actions " Antoine Tremblay
2015-12-04 18:47 ` [PATCH v6 7/7] Enable conditional breakpoints for targets that support software single step " Antoine Tremblay
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