From: Simon Marchi <simon.marchi@polymtl.ca>
To: Stafford Horne <shorne@gmail.com>
Cc: GDB patches <gdb-patches@sourceware.org>,
Openrisc <openrisc@lists.librecores.org>,
Mike Frysinger <vapier@gentoo.org>
Subject: Re: [PATCH v5 3/6] sim: or1k: add or1k target to sim
Date: Mon, 09 Oct 2017 13:33:00 -0000 [thread overview]
Message-ID: <7089df6c-1046-1fd9-150d-1492d4734ac6@polymtl.ca> (raw)
In-Reply-To: <20171009130305.GC2958@lianli.shorne-pla.net>
On 2017-10-09 09:03 AM, Stafford Horne wrote:
>> That code looks strange to me. Enabling byte reordering (SR[LEE]) makes it so that each
>> group of 4 bytes appears swapped in memory? Is this something a program can turn on/off
>> at any time? There isn't much detail about that in the spec it seems.
>
> I have added some more comments to this in the next patch series. I am not
> to sure as to the 'why' for this functionality. But I assume its probably
> to interact with hardware like graphics cards which only support
> little-endian addressing. The SR[LEE] would only be available to change in
> supervisor mode, so not just any program could change it.
>
> The above code only handles the address translation (note for half-word
> access openrisc requires the address to be half-word aligned).
Ok, thanks for the explanation.
> FYI, also the testsuite patch aas a few long lines like:
>
> /* The sign extension produces unexpected results here. */
> SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFFFFFF - 1, 0xFFFF /* 0xFFFF gets sign-extended to 0xFFFFFFFF. */
> SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFF7FFF, 0x8000 /* 0x8000 gets sign-extended to 0xFFFF8000. */
>
> I guess it should be like this? I don't mind the inline comments, but I
> guess convention is convention?
>
> /* 0xFFFF gets sign-extended to 0xFFFFFFFF. */
> SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFFFFFF - 1, 0xFFFF
> /* 0x8000 gets sign-extended to 0xFFFF8000. */
> SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFF7FFF, 0x8000
Personally I prefer with the comment above.
Simon
next prev parent reply other threads:[~2017-10-09 13:33 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-05 13:49 [PATCH v5 0/6] sim port for OpenRISC Stafford Horne
2017-10-05 13:49 ` [PATCH v5 2/6] sim: cgen: add MUL2OFSI and MUL1OFSI macros (needed for OR1K l.mul[u]) Stafford Horne
2017-10-07 16:01 ` Simon Marchi
2017-10-08 12:27 ` Stafford Horne
2017-10-05 13:49 ` [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd]) Stafford Horne
2017-10-07 15:52 ` Simon Marchi
2017-10-08 12:24 ` Stafford Horne
2017-10-08 14:06 ` Simon Marchi
2017-10-05 13:49 ` [PATCH v5 3/6] sim: or1k: add or1k target to sim Stafford Horne
2017-10-07 21:15 ` Simon Marchi
2017-10-09 13:03 ` Stafford Horne
2017-10-09 13:33 ` Simon Marchi [this message]
2017-10-05 13:50 ` [PATCH v5 6/6] sim: testsuite: add testsuite for or1k sim Stafford Horne
2017-10-05 13:57 ` [PATCH v5 0/6] sim port for OpenRISC Stafford Horne
2017-10-05 14:23 ` Stafford Horne
2017-10-09 17:15 [PATCH v5 3/6] sim: or1k: add or1k target to sim Doug Evans via gdb-patches
2017-10-10 23:03 ` Stafford Horne
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