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From: Yao Qi <yao@codesourcery.com>
To: gdb-patches@sourceware.org
Subject: [try 2nd 6/8] Rename some functions to arm_*
Date: Thu, 24 Mar 2011 14:06:00 -0000	[thread overview]
Message-ID: <4D8B4F83.7050207@codesourcery.com> (raw)
In-Reply-To: <4D8B4947.1000000@codesourcery.com>

[-- Attachment #1: Type: text/plain, Size: 152 bytes --]

This patch should be merged to patch 2/8, but `git rebase' failed to
combine them together as a whole.  I sent this separately.

-- 
Yao (齐尧)

[-- Attachment #2: 0006-rename-some-arm-functions.patch --]
[-- Type: text/x-patch, Size: 11313 bytes --]

2011-03-24  Yao Qi  <yao@codesourcery.com>

	* gdb/arm-tdep.c (copy_copro_load_store): Move some common part to ...
	(install_copy_copro_load_store): ... this.  New.
	(arm_copy_copro_load_store): New.
	(copy_undef): Delete.
	(arm_copy_undef): Renamed from copy_undef.
	(decode_misc_memhint_neon): Update caller.
	(decode_unconditional): Likewise.
	(decode_miscellaneous): Likewise.
	(decode_media): Likewise.
	(decode_b_bl_ldmstm): Likewise.
	(decode_ext_reg_ld_st): Delete.
	(arm_decode_ext_reg_ld_st): Renamed from decode_ext_reg_ld_st.
	(decode_svc_copro): Delete.
	(arm_decode_svc_copro): Renamed from decode_svc_copro.
	(arm_process_displaced_insn): Update caller.

---
 gdb/arm-tdep.c |  106 ++++++++++++++++++++++++++++++-------------------------
 1 files changed, 58 insertions(+), 48 deletions(-)

diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index 6ba7b5b..89a6cc4 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -5526,21 +5526,12 @@ cleanup_copro_load_store (struct gdbarch *gdbarch,
     displaced_write_reg (regs, dsc, dsc->u.ldst.rn, rn_val, LOAD_WRITE_PC);
 }
 
-static int
-copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
-		       struct regcache *regs,
-		       struct displaced_step_closure *dsc)
+static void
+install_copy_copro_load_store (struct gdbarch *gdbarch, struct regcache *regs,
+			       struct displaced_step_closure *dsc)
 {
-  unsigned int rn = bits (insn, 16, 19);
   ULONGEST rn_val;
 
-  if (!insn_references_pc (insn, 0x000f0000ul))
-    return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
-
-  if (debug_displaced)
-    fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
-			"load/store insn %.8lx\n", (unsigned long) insn);
-
   /* Coprocessor load/store instructions:
 
      {stc/stc2} [<Rn>, #+/-imm]  (and other immediate addressing modes)
@@ -5550,15 +5541,34 @@ copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
      ldc/ldc2 are handled identically.  */
 
   dsc->tmp[0] = displaced_read_reg (regs, dsc, 0);
-  rn_val = displaced_read_reg (regs, dsc, rn);
+  rn_val = displaced_read_reg (regs, dsc, dsc->u.ldst.rn);
   displaced_write_reg (regs, dsc, 0, rn_val, CANNOT_WRITE_PC);
 
+  dsc->cleanup = &cleanup_copro_load_store;
+}
+
+static int
+arm_copy_copro_load_store (struct gdbarch *gdbarch, uint32_t insn,
+			   struct regcache *regs,
+			   struct displaced_step_closure *dsc)
+{
+  unsigned int rn = bits (insn, 16, 19);
+
+  if (!insn_references_pc (insn, 0x000f0000ul))
+    return arm_copy_unmodified (gdbarch, insn, "copro load/store", dsc);
+
+  if (debug_displaced)
+    fprintf_unfiltered (gdb_stdlog, "displaced: copying coprocessor "
+			"load/store insn %.8lx\n", (unsigned long) insn);
+
+
+
   dsc->u.ldst.writeback = bit (insn, 25);
   dsc->u.ldst.rn = rn;
 
   dsc->modinsn[0] = insn & 0xfff0ffff;
 
-  dsc->cleanup = &cleanup_copro_load_store;
+  install_copy_copro_load_store (gdbarch, regs, dsc);
 
   return 0;
 }
@@ -6906,8 +6916,8 @@ thumb_copy_svc (struct gdbarch *gdbarch, uint16_t insn,
 /* Copy undefined instructions.  */
 
 static int
-copy_undef (struct gdbarch *gdbarch, uint32_t insn,
-	    struct displaced_step_closure *dsc)
+arm_copy_undef (struct gdbarch *gdbarch, uint32_t insn,
+		struct displaced_step_closure *dsc)
 {
   if (debug_displaced)
     fprintf_unfiltered (gdb_stdlog,
@@ -7008,10 +7018,10 @@ decode_misc_memhint_neon (struct gdbarch *gdbarch, uint32_t insn,
       case 0x63: case 0x67: case 0x73: case 0x77:
 	return copy_unpred (gdbarch, insn, dsc);
       default:
-	return copy_undef (gdbarch, insn, dsc);
+	return arm_copy_undef (gdbarch, insn, dsc);
       }
   else
-    return copy_undef (gdbarch, insn, dsc);  /* Probably unreachable.  */
+    return arm_copy_undef (gdbarch, insn, dsc);  /* Probably unreachable.  */
 }
 
 static int
@@ -7038,13 +7048,13 @@ decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
 	{
 	case 0x1: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7:
 	  /* stc/stc2.  */
-	  return copy_copro_load_store (gdbarch, insn, regs, dsc);
+	  return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
 
 	case 0x2:
 	  return arm_copy_unmodified (gdbarch, insn, "mcrr/mcrr2", dsc);
 
 	default:
-	  return copy_undef (gdbarch, insn, dsc);
+	  return arm_copy_undef (gdbarch, insn, dsc);
 	}
 
     case 0x9:
@@ -7054,19 +7064,19 @@ decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
 	  {
 	  case 0x1: case 0x3:
 	    /* ldc/ldc2 imm (undefined for rn == pc).  */
-	    return rn_f ? copy_undef (gdbarch, insn, dsc)
-			: copy_copro_load_store (gdbarch, insn, regs, dsc);
+	    return rn_f ? arm_copy_undef (gdbarch, insn, dsc)
+			: arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
 
 	  case 0x2:
 	    return arm_copy_unmodified (gdbarch, insn, "mrrc/mrrc2", dsc);
 
 	  case 0x4: case 0x5: case 0x6: case 0x7:
 	    /* ldc/ldc2 lit (undefined for rn != pc).  */
-	    return rn_f ? copy_copro_load_store (gdbarch, insn, regs, dsc)
-			: copy_undef (gdbarch, insn, dsc);
+	    return rn_f ? arm_copy_copro_load_store (gdbarch, insn, regs, dsc)
+			: arm_copy_undef (gdbarch, insn, dsc);
 
 	  default:
-	    return copy_undef (gdbarch, insn, dsc);
+	    return arm_copy_undef (gdbarch, insn, dsc);
 	  }
       }
 
@@ -7076,9 +7086,9 @@ decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
     case 0xb:
       if (bits (insn, 16, 19) == 0xf)
         /* ldc/ldc2 lit.  */
-	return copy_copro_load_store (gdbarch, insn, regs, dsc);
+	return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
       else
-	return copy_undef (gdbarch, insn, dsc);
+	return arm_copy_undef (gdbarch, insn, dsc);
 
     case 0xc:
       if (bit (insn, 4))
@@ -7093,7 +7103,7 @@ decode_unconditional (struct gdbarch *gdbarch, uint32_t insn,
 	return arm_copy_unmodified (gdbarch, insn, "cdp/cdp2", dsc);
 
     default:
-      return copy_undef (gdbarch, insn, dsc);
+      return arm_copy_undef (gdbarch, insn, dsc);
     }
 }
 
@@ -7119,21 +7129,21 @@ decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
       else if (op == 0x3)
 	return arm_copy_unmodified (gdbarch, insn, "clz", dsc);
       else
-	return copy_undef (gdbarch, insn, dsc);
+	return arm_copy_undef (gdbarch, insn, dsc);
 
     case 0x2:
       if (op == 0x1)
         /* Not really supported.  */
 	return arm_copy_unmodified (gdbarch, insn, "bxj", dsc);
       else
-	return copy_undef (gdbarch, insn, dsc);
+	return arm_copy_undef (gdbarch, insn, dsc);
 
     case 0x3:
       if (op == 0x1)
 	return arm_copy_bx_blx_reg (gdbarch, insn,
 				regs, dsc);  /* blx register.  */
       else
-	return copy_undef (gdbarch, insn, dsc);
+	return arm_copy_undef (gdbarch, insn, dsc);
 
     case 0x5:
       return arm_copy_unmodified (gdbarch, insn, "saturating add/sub", dsc);
@@ -7146,7 +7156,7 @@ decode_miscellaneous (struct gdbarch *gdbarch, uint32_t insn,
 	return arm_copy_unmodified (gdbarch, insn, "smc", dsc);
 
     default:
-      return copy_undef (gdbarch, insn, dsc);
+      return arm_copy_undef (gdbarch, insn, dsc);
     }
 }
 
@@ -7259,13 +7269,13 @@ decode_media (struct gdbarch *gdbarch, uint32_t insn,
 	    return arm_copy_unmodified (gdbarch, insn, "usada8", dsc);
 	}
       else
-	 return copy_undef (gdbarch, insn, dsc);
+	 return arm_copy_undef (gdbarch, insn, dsc);
 
     case 0x1a: case 0x1b:
       if (bits (insn, 5, 6) == 0x2)  /* op2[1:0].  */
 	return arm_copy_unmodified (gdbarch, insn, "sbfx", dsc);
       else
-	return copy_undef (gdbarch, insn, dsc);
+	return arm_copy_undef (gdbarch, insn, dsc);
 
     case 0x1c: case 0x1d:
       if (bits (insn, 5, 6) == 0x0)  /* op2[1:0].  */
@@ -7276,13 +7286,13 @@ decode_media (struct gdbarch *gdbarch, uint32_t insn,
 	    return arm_copy_unmodified (gdbarch, insn, "bfi", dsc);
 	}
       else
-	return copy_undef (gdbarch, insn, dsc);
+	return arm_copy_undef (gdbarch, insn, dsc);
 
     case 0x1e: case 0x1f:
       if (bits (insn, 5, 6) == 0x2)  /* op2[1:0].  */
 	return arm_copy_unmodified (gdbarch, insn, "ubfx", dsc);
       else
-	return copy_undef (gdbarch, insn, dsc);
+	return arm_copy_undef (gdbarch, insn, dsc);
     }
 
   /* Should be unreachable.  */
@@ -7300,9 +7310,9 @@ decode_b_bl_ldmstm (struct gdbarch *gdbarch, int32_t insn,
 }
 
 static int
-decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
-		      struct regcache *regs,
-		      struct displaced_step_closure *dsc)
+arm_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
+			  struct regcache *regs,
+			  struct displaced_step_closure *dsc)
 {
   unsigned int opcode = bits (insn, 20, 24);
 
@@ -7323,7 +7333,7 @@ decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint32_t insn,
     case 0x11: case 0x15: case 0x19: case 0x1d:  /* vldr.  */
       /* Note: no writeback for these instructions.  Bit 25 will always be
 	 zero though (via caller), so the following works OK.  */
-      return copy_copro_load_store (gdbarch, insn, regs, dsc);
+      return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
     }
 
   /* Should be unreachable.  */
@@ -7368,8 +7378,8 @@ thumb2_decode_ext_reg_ld_st (struct gdbarch *gdbarch, uint16_t insn1,
 }
 
 static int
-decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
-		  struct regcache *regs, struct displaced_step_closure *dsc)
+arm_decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
+		      struct regcache *regs, struct displaced_step_closure *dsc)
 {
   unsigned int op1 = bits (insn, 20, 25);
   int op = bit (insn, 4);
@@ -7377,17 +7387,17 @@ decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
   unsigned int rn = bits (insn, 16, 19);
 
   if ((op1 & 0x20) == 0x00 && (op1 & 0x3a) != 0x00 && (coproc & 0xe) == 0xa)
-    return decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
+    return arm_decode_ext_reg_ld_st (gdbarch, insn, regs, dsc);
   else if ((op1 & 0x21) == 0x00 && (op1 & 0x3a) != 0x00
 	   && (coproc & 0xe) != 0xa)
     /* stc/stc2.  */
-    return copy_copro_load_store (gdbarch, insn, regs, dsc);
+    return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
   else if ((op1 & 0x21) == 0x01 && (op1 & 0x3a) != 0x00
 	   && (coproc & 0xe) != 0xa)
     /* ldc/ldc2 imm/lit.  */
-    return copy_copro_load_store (gdbarch, insn, regs, dsc);
+    return arm_copy_copro_load_store (gdbarch, insn, regs, dsc);
   else if ((op1 & 0x3e) == 0x00)
-    return copy_undef (gdbarch, insn, dsc);
+    return arm_copy_undef (gdbarch, insn, dsc);
   else if ((op1 & 0x3e) == 0x04 && (coproc & 0xe) == 0xa)
     return arm_copy_unmodified (gdbarch, insn, "neon 64bit xfer", dsc);
   else if (op1 == 0x04 && (coproc & 0xe) != 0xa)
@@ -7410,7 +7420,7 @@ decode_svc_copro (struct gdbarch *gdbarch, uint32_t insn, CORE_ADDR to,
   else if ((op1 & 0x30) == 0x30)
     return arm_copy_svc (gdbarch, insn, regs, dsc);
   else
-    return copy_undef (gdbarch, insn, dsc);  /* Possibly unreachable.  */
+    return arm_copy_undef (gdbarch, insn, dsc);  /* Possibly unreachable.  */
 }
 
 static int
@@ -8119,7 +8129,7 @@ arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
       break;
 
     case 0xc: case 0xd: case 0xe: case 0xf:
-      err = decode_svc_copro (gdbarch, insn, to, regs, dsc);
+      err = arm_decode_svc_copro (gdbarch, insn, to, regs, dsc);
       break;
     }
 
-- 
1.7.0.4


  parent reply	other threads:[~2011-03-24 14:05 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-12-25 14:17 [patch 0/3] Displaced stepping for 16-bit Thumb instructions Yao Qi
2010-12-25 14:22 ` [patch 1/3] " Yao Qi
2011-02-17 19:09   ` Ulrich Weigand
2010-12-25 17:09 ` [patch 2/3] " Yao Qi
2011-02-17 19:46   ` Ulrich Weigand
2011-02-18  6:33     ` Yao Qi
2011-02-18 12:18       ` Ulrich Weigand
2011-02-21  7:41         ` Yao Qi
2011-02-21 20:14           ` Ulrich Weigand
2011-02-25 18:09             ` Yao Qi
2011-02-25 20:17               ` Ulrich Weigand
2011-02-26 14:07                 ` Yao Qi
2011-02-28 17:37                   ` Ulrich Weigand
2011-03-01  9:01                     ` Yao Qi
2011-03-01 16:11                       ` Ulrich Weigand
2010-12-25 17:54 ` [patch 3/3] " Yao Qi
2010-12-27 15:15   ` Yao Qi
2011-02-17 20:55   ` Ulrich Weigand
2011-02-18  7:30     ` Yao Qi
2011-02-18 13:25       ` Ulrich Weigand
2011-02-28  2:04     ` Displaced stepping 0003: " Yao Qi
2010-12-29  5:48 ` [patch 0/3] Displaced stepping " Yao Qi
2011-01-13 12:38 ` Yao Qi
2011-02-10  6:48 ` Ping 2 " Yao Qi
2011-02-26 17:50 ` Displaced stepping 0002: refactor and create some copy helpers Yao Qi
2011-02-28 17:53   ` Ulrich Weigand
2011-02-28  2:15 ` Displaced stepping 0004: wip: 32-bit Thumb instructions Yao Qi
2011-03-24 13:49 ` [try 2nd 0/8] Displaced stepping for " Yao Qi
2011-03-24 13:56   ` [try 2nd 1/8] Fix cleanup_branch to take Thumb into account Yao Qi
2011-04-06 20:46     ` Ulrich Weigand
2011-04-07  3:45       ` Yao Qi
2011-03-24 13:58   ` [try 2nd 2/8] Rename copy_* functions to arm_copy_* Yao Qi
2011-04-06 20:51     ` Ulrich Weigand
2011-04-07  8:02       ` Yao Qi
2011-04-19  9:07         ` Yao Qi
2011-04-26 17:09         ` Ulrich Weigand
2011-04-27 10:27           ` Yao Qi
2011-04-27 13:32             ` Ulrich Weigand
2011-04-28  5:05               ` Yao Qi
2011-03-24 14:01   ` [try 2nd 3/8] Refactor copy_svc_os Yao Qi
2011-04-06 20:55     ` Ulrich Weigand
2011-04-07  4:19       ` Yao Qi
2011-03-24 14:05   ` [try 2nd 5/8] Displaced stepping for Thumb 32-bit insns Yao Qi
2011-05-05 13:25     ` Yao Qi
2011-05-17 17:14       ` Ulrich Weigand
2011-05-23 11:32         ` Yao Qi
2011-05-23 11:32         ` Yao Qi
2011-05-27 22:11           ` Ulrich Weigand
2011-07-06 10:55         ` Yao Qi
2011-07-15 19:57           ` Ulrich Weigand
2011-07-18  9:26             ` Yao Qi
2011-03-24 14:05   ` [try 2nd 4/8] Displaced stepping for Thumb 16-bit insn Yao Qi
2011-05-05 13:24     ` Yao Qi
2011-05-10 13:58       ` Ulrich Weigand
2011-05-11 13:06         ` Yao Qi
2011-05-16 17:19           ` Ulrich Weigand
2011-05-17 14:29             ` Yao Qi
2011-05-17 17:20               ` Ulrich Weigand
2011-03-24 14:06   ` Yao Qi [this message]
2011-04-06 20:52     ` [try 2nd 6/8] Rename some functions to arm_* Ulrich Weigand
2011-04-07  4:26       ` Yao Qi
2011-03-24 14:11   ` [try 2nd 7/8] Test case Yao Qi
2011-05-05 13:26     ` Yao Qi
2011-05-11 13:15       ` [try 2nd 7/8] Test case: V3 Yao Qi
2011-05-17 17:24         ` Ulrich Weigand
2011-03-24 15:14   ` [try 2nd 8/8] NEWS Yao Qi

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