From: "Jan Beulich" <JBeulich@novell.com>
To: <gdb-patches@sourceware.org>
Cc: "Richard Henderson" <rth@twiddle.net>
Subject: [PATCH] x86 CFI extensions
Date: Tue, 13 Sep 2005 16:17:00 -0000 [thread overview]
Message-ID: <432717DB.76F0.0078.0@novell.com> (raw)
In-Reply-To: <20050912074914.GA31047@twiddle.net>
[-- Attachment #1: Type: text/plain, Size: 3521 bytes --]
>>> Richard Henderson <rth@twiddle.net> 12.09.05 09:49:14 >>>
>On Mon, Sep 12, 2005 at 09:04:12AM +0200, Jan Beulich wrote:
>> But truly I think the processor-specific pieces of Dwarf's
>> frame unwind spec should provide numbering for the complete set of
>> registers.
>
>Except there is no standards body for this. So *someone* will
>have to make it up.
>
>Make it up and put it in gas and gdb: that will make it a defacto
standard.
This adds to gdb a little more than the minimum set of registers
needed
to at least fully understand CFI annotations for Linux' pt_regs.
Built and tested on i686-pc-linux-gnu and x86_64-unknown-linux-gnu.
Jan
gdb/
2005-09-13 Jan Beulich <jbeulich@novell.com>
* amd64-tdep.h (AMD64_FCTRL_REGNUM, AMD64_FSTAT_REGNUM,
AMD64_MXCSR_REGNUM): New.
* amd64-tdep.c (amd64_dwarf_regmap): Add eflags, selector regs,
mxcsr, fp control and status words.
* i386-tdep.c (): Add selector regs, mxcsr, fp control and
status
words.
---
/home/jbeulich/src/gdb/mainline/2005-09-13/gdb/amd64-tdep.c 2005-07-05
09:09:52.000000000 +0200
+++ 2005-09-13/gdb/amd64-tdep.c 2005-09-13 17:50:00.723239944
+0200
@@ -212,7 +212,35 @@ static int amd64_dwarf_regmap[] =
AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
- AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7
+ AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
+
+ /* Control and Status Flags Register. */
+ AMD64_EFLAGS_REGNUM,
+
+ /* Selector Registers. */
+ AMD64_ES_REGNUM,
+ AMD64_CS_REGNUM,
+ AMD64_SS_REGNUM,
+ AMD64_DS_REGNUM,
+ AMD64_FS_REGNUM,
+ AMD64_GS_REGNUM,
+ -1,
+ -1,
+
+ /* Segment Base Address Registers. */
+ -1,
+ -1,
+ -1,
+ -1,
+
+ /* Special Selector Registers. */
+ -1,
+ -1,
+
+ /* Floating Point Control Registers. */
+ AMD64_MXCSR_REGNUM,
+ AMD64_FCTRL_REGNUM,
+ AMD64_FSTAT_REGNUM
};
static const int amd64_dwarf_regmap_len =
---
/home/jbeulich/src/gdb/mainline/2005-09-13/gdb/amd64-tdep.h 2004-04-12
18:17:20.000000000 +0200
+++ 2005-09-13/gdb/amd64-tdep.h 2005-09-13 15:41:55.000000000
+0200
@@ -52,8 +52,11 @@ enum amd64_regnum
AMD64_FS_REGNUM, /* %fs */
AMD64_GS_REGNUM, /* %gs */
AMD64_ST0_REGNUM = 24, /* %st0 */
+ AMD64_FCTRL_REGNUM = AMD64_ST0_REGNUM + 8,
+ AMD64_FSTAT_REGNUM = AMD64_ST0_REGNUM + 9,
AMD64_XMM0_REGNUM = 40, /* %xmm0 */
- AMD64_XMM1_REGNUM /* %xmm1 */
+ AMD64_XMM1_REGNUM, /* %xmm1 */
+ AMD64_MXCSR_REGNUM = AMD64_XMM0_REGNUM + 16
};
/* Number of general purpose registers. */
---
/home/jbeulich/src/gdb/mainline/2005-09-13/gdb/i386-tdep.c 2005-07-26
08:26:49.000000000 +0200
+++ 2005-09-13/gdb/i386-tdep.c 2005-09-13 11:46:18.000000000 +0200
@@ -225,12 +225,25 @@ i386_svr4_reg_to_regnum (int reg)
/* Floating-point registers. */
return reg - 11 + I387_ST0_REGNUM;
}
- else if (reg >= 21)
+ else if (reg >= 21 && reg <= 36)
{
/* The SSE and MMX registers have the same numbers as with dbx.
*/
return i386_dbx_reg_to_regnum (reg);
}
+ switch (reg)
+ {
+ case 37: return I387_FCTRL_REGNUM;
+ case 38: return I387_FSTAT_REGNUM;
+ case 39: return I387_MXCSR_REGNUM;
+ case 40: return I386_ES_REGNUM;
+ case 41: return I386_CS_REGNUM;
+ case 42: return I386_SS_REGNUM;
+ case 43: return I386_DS_REGNUM;
+ case 44: return I386_FS_REGNUM;
+ case 45: return I386_GS_REGNUM;
+ }
+
/* This will hopefully provoke a warning. */
return NUM_REGS + NUM_PSEUDO_REGS;
}
[-- Attachment #2: gdb-mainline-x86-cfi-extensions.patch --]
[-- Type: application/octet-stream, Size: 3083 bytes --]
This adds to gdb a little more than the minimum set of registers needed
to at least fully understand CFI annotations for Linux' pt_regs.
Built and tested on i686-pc-linux-gnu and x86_64-unknown-linux-gnu.
Jan
gdb/
2005-09-13 Jan Beulich <jbeulich@novell.com>
* amd64-tdep.h (AMD64_FCTRL_REGNUM, AMD64_FSTAT_REGNUM,
AMD64_MXCSR_REGNUM): New.
* amd64-tdep.c (amd64_dwarf_regmap): Add eflags, selector regs,
mxcsr, fp control and status words.
* i386-tdep.c (): Add selector regs, mxcsr, fp control and status
words.
--- /home/jbeulich/src/gdb/mainline/2005-09-13/gdb/amd64-tdep.c 2005-07-05 09:09:52.000000000 +0200
+++ 2005-09-13/gdb/amd64-tdep.c 2005-09-13 17:50:00.723239944 +0200
@@ -212,7 +212,35 @@ static int amd64_dwarf_regmap[] =
AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1,
AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3,
AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5,
- AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7
+ AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7,
+
+ /* Control and Status Flags Register. */
+ AMD64_EFLAGS_REGNUM,
+
+ /* Selector Registers. */
+ AMD64_ES_REGNUM,
+ AMD64_CS_REGNUM,
+ AMD64_SS_REGNUM,
+ AMD64_DS_REGNUM,
+ AMD64_FS_REGNUM,
+ AMD64_GS_REGNUM,
+ -1,
+ -1,
+
+ /* Segment Base Address Registers. */
+ -1,
+ -1,
+ -1,
+ -1,
+
+ /* Special Selector Registers. */
+ -1,
+ -1,
+
+ /* Floating Point Control Registers. */
+ AMD64_MXCSR_REGNUM,
+ AMD64_FCTRL_REGNUM,
+ AMD64_FSTAT_REGNUM
};
static const int amd64_dwarf_regmap_len =
--- /home/jbeulich/src/gdb/mainline/2005-09-13/gdb/amd64-tdep.h 2004-04-12 18:17:20.000000000 +0200
+++ 2005-09-13/gdb/amd64-tdep.h 2005-09-13 15:41:55.000000000 +0200
@@ -52,8 +52,11 @@ enum amd64_regnum
AMD64_FS_REGNUM, /* %fs */
AMD64_GS_REGNUM, /* %gs */
AMD64_ST0_REGNUM = 24, /* %st0 */
+ AMD64_FCTRL_REGNUM = AMD64_ST0_REGNUM + 8,
+ AMD64_FSTAT_REGNUM = AMD64_ST0_REGNUM + 9,
AMD64_XMM0_REGNUM = 40, /* %xmm0 */
- AMD64_XMM1_REGNUM /* %xmm1 */
+ AMD64_XMM1_REGNUM, /* %xmm1 */
+ AMD64_MXCSR_REGNUM = AMD64_XMM0_REGNUM + 16
};
/* Number of general purpose registers. */
--- /home/jbeulich/src/gdb/mainline/2005-09-13/gdb/i386-tdep.c 2005-07-26 08:26:49.000000000 +0200
+++ 2005-09-13/gdb/i386-tdep.c 2005-09-13 11:46:18.000000000 +0200
@@ -225,12 +225,25 @@ i386_svr4_reg_to_regnum (int reg)
/* Floating-point registers. */
return reg - 11 + I387_ST0_REGNUM;
}
- else if (reg >= 21)
+ else if (reg >= 21 && reg <= 36)
{
/* The SSE and MMX registers have the same numbers as with dbx. */
return i386_dbx_reg_to_regnum (reg);
}
+ switch (reg)
+ {
+ case 37: return I387_FCTRL_REGNUM;
+ case 38: return I387_FSTAT_REGNUM;
+ case 39: return I387_MXCSR_REGNUM;
+ case 40: return I386_ES_REGNUM;
+ case 41: return I386_CS_REGNUM;
+ case 42: return I386_SS_REGNUM;
+ case 43: return I386_DS_REGNUM;
+ case 44: return I386_FS_REGNUM;
+ case 45: return I386_GS_REGNUM;
+ }
+
/* This will hopefully provoke a warning. */
return NUM_REGS + NUM_PSEUDO_REGS;
}
next parent reply other threads:[~2005-09-13 16:17 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <432070850200007800024465@emea1-mh.id2.novell.com>
[not found] ` <20050908154645.GN3966@smtp.west.cox.net>
[not found] ` <43207BA30200007800024502@emea1-mh.id2.novell.com>
[not found] ` <20050908161334.GP3966@smtp.west.cox.net>
[not found] ` <43214D2D02000078000247B5@emea1-mh.id2.novell.com>
[not found] ` <20050910055836.GA28662@twiddle.net>
[not found] ` <4325448C0200007800024DF5@emea1-mh.id2.novell.com>
[not found] ` <20050912074914.GA31047@twiddle.net>
2005-09-13 16:17 ` Jan Beulich [this message]
2005-09-17 20:59 ` Daniel Jacobowitz
2005-09-17 22:32 ` Mark Kettenis
2005-09-17 22:40 ` Daniel Jacobowitz
2005-09-19 7:26 ` Jan Beulich
2005-09-21 20:02 ` Mark Kettenis
2005-09-22 8:22 ` Richard Henderson
2005-09-22 12:48 ` Daniel Jacobowitz
2005-09-23 7:42 Jan Beulich
2005-09-23 8:03 ` Eli Zaretskii
2005-09-23 12:57 ` Daniel Jacobowitz
2005-09-26 1:24 ` Daniel Jacobowitz
2005-09-26 7:04 ` Jan Beulich
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