Re: STEP_SKIPS_DELAY question, sort of

[Orjan Friberg <orjan.friberg@axis.com>]

Orjan Friberg wrote:
> Andrew Cagney wrote:
>>
>> I also think this needs a new macro name that better reflects what the 
>> test is doing.  But I've no good ideas :-/ (SINGLE_STEP_THROUGH_DELAY 
>> (pc)?)

I'm facing a slightly different situation than the MIPS case when implementing 
SINGLE_STEP_THROUGH_DELAY, because the size of the instruction that the delay 
slot belongs to may be 2, 4, or 6 bytes.  (For MIPS, it seems the size of that 
instruction is always 4 bytes.)

So, I have to find out the size of the preceding instruction (since I want to do 
the single-step thingy when we're stopped in the delay slot), but I can't find 
anything in the opcodes directory that would let me do that.

The thing is, this information (whether I'm in a delay slot, and the address of 
the instruction the delay slot belongs to) is available in a register.  Besides 
the fact that this triggers sending a 'g' packet to the remote target, is it 
wrong to deduce this information from the registers content rather than reading 
from the program's text segment?

Basically, my implementation would look like this:

int
cris_single_step_through_delay (CORE_ADDR pc)
{
   ULONGEST erp;
   int ret = 0;
   regcache_cooked_read_unsigned (current_regcache, ERP_REGNUM, &erp);
   if (erp & 0x1)
     /* In delay slot - check if there's a breakpoint at the preceding
        instruction.  */
     if (breakpoint_here_p (erp & ~0x1))
       ret = 1;
   return ret;
}

-- 
Orjan Friberg
Axis Communications