Re: [PATCH] gdb/riscv: Improve flen length determiniation

[Andrew Burgess <andrew.burgess@embecosm.com>]

* Simon Cook <simon.cook@embecosm.com> [2019-05-22 12:37:45 +0100]:

> This solves an assertion failure when a remote provides a target
> description which only refers to floating point registers by their
> hardware name (e.g. f0), rather than their ABI name (e.g. ft0). GDB
> assumed that should the floating point register feature be presented,
> it would contain a register called ft0.
> 
> The floating point length is now instead determined by searching for
> the same register, but looking for any of its aliases.
> 
> gdb/ChangeLog:
> 
> 	* riscv-tdep.c (riscv_gdbarch_init): Support determining flen from
> 	target descriptions using exclusively floating point register name
> 	aliases.

Thanks for looking at this.

I've pushed your patch to master.

Thanks,
Andrew


> ---
>  gdb/ChangeLog    |  6 ++++++
>  gdb/riscv-tdep.c | 17 ++++++++++++++++-
>  2 files changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
> index 4fe07ef437..072c8e3720 100644
> --- a/gdb/riscv-tdep.c
> +++ b/gdb/riscv-tdep.c
> @@ -3094,7 +3094,22 @@ riscv_gdbarch_init (struct gdbarch_info info,
>        valid_p &= riscv_check_tdesc_feature (tdesc_data, feature_fpu,
>                                              &riscv_freg_feature);
>  
> -      int bitsize = tdesc_register_bitsize (feature_fpu, "ft0");
> +      /* Search for the first floating point register (by any alias), to
> +         determine the bitsize.  */
> +      int bitsize = -1;
> +      const auto &fp0 = riscv_freg_feature.registers[0];
> +
> +      for (const char *name : fp0.names)
> +	{
> +	  if (tdesc_unnumbered_register (feature_fpu, name))
> +	    {
> +	      bitsize = tdesc_register_bitsize (feature_fpu, name);
> +	      break;
> +	    }
> +	}
> +
> +      gdb_assert (bitsize != -1);
> +
>        features.flen = (bitsize / 8);
>  
>        if (riscv_debug_gdbarch)
> -- 
> 2.17.1
>