From: Joel Brobecker <brobecker@adacore.com>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: andrew.burgess@embecosm.com, gdb-patches@sourceware.org,
Jim Wilson <jimw@sifive.com>
Subject: Re: [PATCH] gdb/riscv: Improve non-dwarf stack unwinding
Date: Wed, 26 Sep 2018 19:15:00 -0000 [thread overview]
Message-ID: <20180926191514.GA2448@adacore.com> (raw)
In-Reply-To: <mhng-06926dec-9f45-4801-a163-690cc865274b@palmer-si-x1c4>
> While I agree this is true for I-based ISAs, I think this might be able to
> fire for E-based ISAs because those can actually encode invalid register
> indices. That said, these should be decoded as invalid instructions so I
> think we're safe here. I'm OK either way (ie, abort or warn).
And FWIW, I agree that should the register number be invalid
in the instruction, the error should be reported during the decoding.
So the asserts here are good.
--
Joel
prev parent reply other threads:[~2018-09-26 19:15 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-19 16:41 Andrew Burgess
2018-09-21 16:20 ` Palmer Dabbelt
2018-09-26 13:13 ` PING: " Andrew Burgess
2018-09-26 13:49 ` Joel Brobecker
2018-09-26 15:11 ` Andrew Burgess
2018-09-26 16:53 ` Joel Brobecker
2018-09-26 17:13 ` Palmer Dabbelt
2018-09-26 19:15 ` Joel Brobecker [this message]
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