[PATCH master+7.12] [AArch64] Match instruction "STP with base register" in prologue

[PATCH master+7.12] [AArch64] Match instruction "STP with base register" in prologue

[Yao Qi]

Nowadays, we only match pre-indexed STP in prologue.  Due to the change
in gcc, https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01933.html, it
may generate "STP with base register" in prologue, which GDB doesn't
handle.  That is to say, previously GCC generates prologue like this,

 sub sp, sp, #490
 stp x29, x30, [sp, #-96]!
 mov x29, sp

with the gcc patch above, GCC generates prologue like like this,

 sub sp, sp, #4f0
 stp x29, x30, [sp]
 mov x29, sp

This patch is to teach GDB to recognize this instruction in prologue
analysis.  It fixes some fails in gdb.base/break-interp.exp.
Regression tested on aarch64-linux with GCC mainline and 4.9.3.
I'll push it in.

gdb:

2016-08-19  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_analyze_prologue): Handle register
	based STP instruction.
---
 gdb/aarch64-tdep.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index e97e2f4..3b7e954 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -322,10 +322,11 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
 			 is64 ? 8 : 4, regs[rt]);
 	}
       else if ((inst.opcode->iclass == ldstpair_off
-		|| inst.opcode->iclass == ldstpair_indexed)
-	       && inst.operands[2].addr.preind
+		|| (inst.opcode->iclass == ldstpair_indexed
+		    && inst.operands[2].addr.preind))
 	       && strcmp ("stp", inst.opcode->name) == 0)
 	{
+	  /* STP with addressing mode Pre-indexed and Base register.  */
 	  unsigned rt1 = inst.operands[0].reg.regno;
 	  unsigned rt2 = inst.operands[1].reg.regno;
 	  unsigned rn = inst.operands[2].addr.base_regno;
-- 
1.9.1

aarch64 regression: gdb.cp/nextoverthrow.exp [Re: [PATCH master+7.12] [AArch64] Match instruction "STP with base register" in prologue]

[Jan Kratochvil]

On Fri, 19 Aug 2016 15:34:36 +0200, Yao Qi wrote:
> I'll push it in.
[...]
> 2016-08-19  Yao Qi  <yao.qi@linaro.org>
> 
> 	* aarch64-tdep.c (aarch64_analyze_prologue): Handle register
> 	based STP instruction.

03bcd7394eefb9399f5ab97919a0463dea274c02 is the first bad commit
commit 03bcd7394eefb9399f5ab97919a0463dea274c02
Author: Yao Qi <yao.qi@linaro.org>
Date:   Fri Aug 19 14:49:31 2016 +0100
    [AArch64] Match instruction "STP with base register" in prologue

FAIL: gdb.cp/nextoverthrow.exp: tbreak _Unwind_RaiseException (GDB internal error)
FAIL: gdb.cp/nextoverthrow.exp: continuing to _Unwind_RaiseException (the program exited)
FAIL: gdb.cp/nextoverthrow.exp: finish (the program is no longer running)
FAIL: gdb.cp/nextoverthrow.exp: continuing to Second: resumebpt (the program is no longer running)
FAIL: gdb.cp/nextoverthrow.exp: continuing to done (the program is no longer running)
FAIL: gdb.cp/nextoverthrow.exp: post-check - advance

tbreak _Unwind_RaiseException^M
aarch64-tdep.c:335: internal-error: CORE_ADDR aarch64_analyze_prologue(gdbarch*, CORE_ADDR, CORE_ADDR, aarch64_prologue_cache*): Assertion `inst.operands[0].type == AARCH64_OPND_Rt' failed.^M
A problem internal to GDB has been detected,^M
further debugging may prove unreliable.^M
Quit this debugging session? (y or n) FAIL: gdb.cp/nextoverthrow.exp: tbreak _Unwind_RaiseException (GDB internal error)

RHEL-7.3-20161007.n.0 Server aarch64
gcc-4.8.5-11.el7.aarch64

Please contact me (possibly also offlist) if you have it unreproducible.


Thanks,
Jan

Re: aarch64 regression: gdb.cp/nextoverthrow.exp [Re: [PATCH master+7.12] [AArch64] Match instruction "STP with base register" in prologue]

[Yao Qi]

Hi Jan,

On Mon, Oct 10, 2016 at 9:41 PM, Jan Kratochvil
> tbreak _Unwind_RaiseException^M
> aarch64-tdep.c:335: internal-error: CORE_ADDR aarch64_analyze_prologue(gdbarch*, CORE_ADDR, CORE_ADDR, aarch64_prologue_cache*): Assertion `inst.operands[0].type == AARCH64_OPND_Rt' failed.^M
> A problem internal to GDB has been detected,^M
> further debugging may prove unreliable.^M
> Quit this debugging session? (y or n) FAIL: gdb.cp/nextoverthrow.exp: tbreak _Unwind_RaiseException (GDB internal error)
>
> RHEL-7.3-20161007.n.0 Server aarch64
> gcc-4.8.5-11.el7.aarch64
>
> Please contact me (possibly also offlist) if you have it unreproducible.
>

This internal error is caused by instruction "stp with FP registers" in
the prologue.  The instruction triggers this assert is like
"stp d8, d9, [sp, #imm]".  However, aarch64 gdb doesn't track FP registers
at all in prologue analysis.

Could you open a ticket in bugzilla for this error?  I am testing a patch.

-- 
Yao (齐尧)

Re: aarch64 regression: gdb.cp/nextoverthrow.exp [Re: [PATCH master+7.12] [AArch64] Match instruction "STP with base register" in prologue]

[Jan Kratochvil]

On Tue, 11 Oct 2016 13:25:31 +0200, Yao Qi wrote:
> Could you open a ticket in bugzilla for this error?  I am testing a patch.

https://sourceware.org/bugzilla/show_bug.cgi?id=20682


Thanks,
Jan

Re: aarch64 regression: gdb.cp/nextoverthrow.exp [Re: [PATCH master+7.12] [AArch64] Match instruction "STP with base register" in prologue]

[Yao Qi]

Jan Kratochvil <jan.kratochvil@redhat.com> writes:

>> Could you open a ticket in bugzilla for this error?  I am testing a patch.
>
> https://sourceware.org/bugzilla/show_bug.cgi?id=20682

Thanks, here is the patch...

-- 
Yao (齐尧)

From 5794d10bcda63da8fc47d0a76c29669af83ed48b Mon Sep 17 00:00:00 2001
From: Yao Qi <yao.qi@linaro.org>
Date: Tue, 11 Oct 2016 12:12:46 +0100
Subject: [PATCH] [AArch64] Track FP registers in prologue analyzer

We don't track FP registers in aarch64 prologue analyzer, so this causes
an internal error when FP registers are saved by "stp" instruction in
prologue (stp	d8, d9, [sp,#128]),

 tbreak _Unwind_RaiseException^M
 aarch64-tdep.c:335: internal-error: CORE_ADDR aarch64_analyze_prologue(gdbarch*, CORE_ADDR, CORE_ADDR, aarch64_prologue_cache*): Assertion `inst.operands[0].type == AARCH64_OPND_Rt' failed.^M
 A problem internal to GDB has been detected,

This patch teaches GDB to track FP registers (D registers) in prologue
analyzer.

gdb:

2016-10-12  Yao Qi  <yao.qi@linaro.org>

	PR tdep/20682
	* aarch64-tdep.c: Replace 32 with AARCH64_D_REGISTER_COUNT.
	(aarch64_analyze_prologue): Extend array 'regs' for D registers.
	Assert that operand 0 and 1 can be X or D registers.  Update
	register number for D registers.  Update registers in frame
	cache.
	* aarch64-tdep.h (AARCH64_D_REGISTER_COUNT): New macro.

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 16dd365..be72785 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -68,7 +68,7 @@
 
 /* Pseudo register base numbers.  */
 #define AARCH64_Q0_REGNUM 0
-#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + 32)
+#define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT)
 #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32)
 #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32)
 #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32)
@@ -206,11 +206,12 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
 {
   enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch);
   int i;
-  pv_t regs[AARCH64_X_REGISTER_COUNT];
+  /* Track X registers and D registers in prologue.  */
+  pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT];
   struct pv_area *stack;
   struct cleanup *back_to;
 
-  for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++)
+  for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++)
     regs[i] = pv_register (i, 0);
   stack = make_pv_area (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch));
   back_to = make_cleanup_free_pv_area (stack);
@@ -328,13 +329,15 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
 	       && strcmp ("stp", inst.opcode->name) == 0)
 	{
 	  /* STP with addressing mode Pre-indexed and Base register.  */
-	  unsigned rt1 = inst.operands[0].reg.regno;
-	  unsigned rt2 = inst.operands[1].reg.regno;
+	  unsigned rt1;
+	  unsigned rt2;
 	  unsigned rn = inst.operands[2].addr.base_regno;
 	  int32_t imm = inst.operands[2].addr.offset.imm;
 
-	  gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt);
-	  gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2);
+	  gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt
+		      || inst.operands[0].type == AARCH64_OPND_Ft);
+	  gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2
+		      || inst.operands[1].type == AARCH64_OPND_Ft2);
 	  gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7);
 	  gdb_assert (!inst.operands[2].addr.offset.is_reg);
 
@@ -349,6 +352,17 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
 					 pv_add_constant (regs[rn], imm + 8)))
 	    break;
 
+	  rt1 = inst.operands[0].reg.regno;
+	  rt2 = inst.operands[1].reg.regno;
+	  if (inst.operands[0].type == AARCH64_OPND_Ft)
+	    {
+	      /* Only bottom 64-bit of each V register (D register) need
+		 to be preserved.  */
+	      gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D);
+	      rt1 += AARCH64_X_REGISTER_COUNT;
+	      rt2 += AARCH64_X_REGISTER_COUNT;
+	    }
+
 	  pv_area_store (stack, pv_add_constant (regs[rn], imm), 8,
 			 regs[rt1]);
 	  pv_area_store (stack, pv_add_constant (regs[rn], imm + 8), 8,
@@ -408,6 +422,16 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
 	cache->saved_regs[i].addr = offset;
     }
 
+  for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++)
+    {
+      int regnum = gdbarch_num_regs (gdbarch);
+      CORE_ADDR offset;
+
+      if (pv_area_find_reg (stack, gdbarch, i + AARCH64_X_REGISTER_COUNT,
+			    &offset))
+	cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].addr = offset;
+    }
+
   do_cleanups (back_to);
   return start;
 }
diff --git a/gdb/aarch64-tdep.h b/gdb/aarch64-tdep.h
index a95b613..6252820 100644
--- a/gdb/aarch64-tdep.h
+++ b/gdb/aarch64-tdep.h
@@ -68,6 +68,8 @@ enum aarch64_regnum
 
 /* Total number of general (X) registers.  */
 #define AARCH64_X_REGISTER_COUNT 32
+/* Total number of D registers.  */
+#define AARCH64_D_REGISTER_COUNT 32
 
 /* The maximum number of modified instructions generated for one
    single-stepped instruction.  */