* [PATCH] sim: bfin: fix corner case Logical shift issues
@ 2012-03-19 5:05 Mike Frysinger
2012-03-19 5:18 ` [PATCH] sim: bfin: add tests for new shift behavior Mike Frysinger
2012-03-19 5:26 ` Mike Frysinger
0 siblings, 2 replies; 3+ messages in thread
From: Mike Frysinger @ 2012-03-19 5:05 UTC (permalink / raw)
To: gdb-patches; +Cc: Robin Getz
From: Robin Getz <robin.getz@analog.com>
Overflow with shift operations happens independently of saturation, but
we have the logic merged. Extend the lshift function so that callers
can tell it when to handle each independently, and then do so when it's
needed.
Committed.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-03-19 Robin Getz <robin.getz@analog.com>
* bfin-sim.c (lshift): Add an overflow flag. Delete now unused
i, j, and tmp vars. Add a new v_i var. Split the overflow logic
out from the saturate logic. Do not set V ASTAT bits when working
with accumulators.
(decode_ALU2op_0): Add new argument to lshift call.
(decode_LOGI2op_0, decode_dsp32shift_0, decode_dsp32shiftimm_0):
Likewise.
---
sim/bfin/bfin-sim.c | 98 +++++++++++++++++++++++++++-----------------------
1 files changed, 53 insertions(+), 45 deletions(-)
diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c
index ef7362b..2c93e04 100644
--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -748,12 +748,12 @@ lshiftrt (SIM_CPU *cpu, bu64 val, int cnt, int size)
}
static bu64
-lshift (SIM_CPU *cpu, bu64 val, int cnt, int size, bool saturate)
+lshift (SIM_CPU *cpu, bu64 val, int cnt, int size, bool saturate, bool overflow)
{
- int i, j, real_cnt = cnt > size ? size : cnt;
+ int v_i, real_cnt = cnt > size ? size : cnt;
bu64 sgn = ~((val >> (size - 1)) - 1);
int mask_cnt = size - 1;
- bu64 masked, new_val = val, tmp;
+ bu64 masked, new_val = val;
bu64 mask = ~0;
mask <<= mask_cnt;
@@ -777,31 +777,35 @@ lshift (SIM_CPU *cpu, bu64 val, int cnt, int size, bool saturate)
However, it's a little more complex than looking at sign bits, we need
to see if we are shifting the sign information away... */
- tmp = val & ((~mask << 1) | 1);
-
- j = 0;
- for (i = 1; i <= real_cnt && saturate; i++)
- {
- if ((tmp & ((bu64)1 << (size - 1))) !=
- (((val >> mask_cnt) & 0x1) << mask_cnt))
- j++;
- tmp <<= 1;
- }
- saturate &= (!sgn && (new_val & (1 << mask_cnt)))
- || (sgn && !(new_val & (1 << mask_cnt)));
+ if (((val << cnt) >> size) == 0
+ || (((val << cnt) >> size) == ~(~0 << cnt)
+ && ((new_val >> (size - 1)) & 0x1)))
+ v_i = 0;
+ else
+ v_i = 1;
switch (size)
{
case 16:
- if (j || (saturate && (new_val & mask)))
- new_val = sgn == 0 ? 0x7fff : 0x8000, saturate = 1;
new_val &= 0xFFFF;
+ if (saturate && (v_i || ((val >> (size - 1)) != (new_val >> (size - 1)))))
+ {
+ new_val = (val >> (size - 1)) == 0 ? 0x7fff : 0x8000;
+ v_i = 1;
+ }
break;
case 32:
new_val &= 0xFFFFFFFF;
masked &= 0xFFFFFFFF;
- if (j || (saturate && ((sgn != masked) || (!sgn && new_val == 0))))
- new_val = sgn == 0 ? 0x7fffffff : 0x80000000, saturate = 1;
+ sgn &= 0xFFFFFFFF;
+ if (saturate
+ && (v_i
+ || (sgn != masked)
+ || (!sgn && new_val == 0 && val != 0)))
+ {
+ new_val = sgn == 0 ? 0x7fffffff : 0x80000000;
+ v_i = 1;
+ }
break;
case 40:
new_val &= 0xFFFFFFFFFFull;
@@ -814,9 +818,13 @@ lshift (SIM_CPU *cpu, bu64 val, int cnt, int size, bool saturate)
SET_ASTATREG (an, new_val >> (size - 1));
SET_ASTATREG (az, new_val == 0);
- SET_ASTATREG (v, !!(saturate || j));
- if (saturate || j)
- SET_ASTATREG (vs, 1);
+ if (size != 40)
+ {
+ SET_ASTATREG (v, overflow && v_i);
+ if (overflow && v_i)
+ SET_ASTATREG (vs, 1);
+ }
+
return new_val;
}
@@ -2557,7 +2565,7 @@ decode_ALU2op_0 (SIM_CPU *cpu, bu16 iw0)
else if (opc == 2)
{
TRACE_INSN (cpu, "R%i <<= R%i;", dst, src);
- SET_DREG (dst, lshift (cpu, DREG (dst), DREG (src), 32, 0));
+ SET_DREG (dst, lshift (cpu, DREG (dst), DREG (src), 32, 0, 0));
}
else if (opc == 3)
{
@@ -2760,7 +2768,7 @@ decode_LOGI2op_0 (SIM_CPU *cpu, bu16 iw0)
TRACE_INSN (cpu, "R%i <<= %s;", dst, uimm_str);
if (INSN_LEN == 8)
illegal_instruction_combination (cpu);
- SET_DREG (dst, lshift (cpu, DREG (dst), uimm, 32, 0));
+ SET_DREG (dst, lshift (cpu, DREG (dst), uimm, 32, 0, 0));
}
}
@@ -5158,7 +5166,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
if (shft <= 0)
val = ashiftrt (cpu, val, -shft, 16);
else
- val = lshift (cpu, val, shft, 16, sop == 1);
+ val = lshift (cpu, val, shft, 16, sop == 1, 1);
if ((HLs & 2) == 0)
STORE (DREG (dst0), REG_H_L (DREG (dst0), val));
@@ -5219,7 +5227,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
if (shft <= 0)
val = ashiftrt (cpu, val, -shft, 40);
else
- val = lshift (cpu, val, shft, 40, 0);
+ val = lshift (cpu, val, shft, 40, 0, 0);
STORE (AXREG (HLs), (val >> 32) & 0xff);
STORE (AWREG (HLs), (val & 0xffffffff));
@@ -5239,7 +5247,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
if (shft <= 0)
val = lshiftrt (cpu, val, -shft, 40);
else
- val = lshift (cpu, val, shft, 40, 0);
+ val = lshift (cpu, val, shft, 40, 0, 0);
STORE (AXREG (HLs), (val >> 32) & 0xff);
STORE (AWREG (HLs), (val & 0xffffffff));
@@ -5267,9 +5275,9 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
}
else
{
- val0 = lshift (cpu, val0, shft, 16, sop == 1);
+ val0 = lshift (cpu, val0, shft, 16, sop == 1, 1);
astat = ASTAT;
- val1 = lshift (cpu, val1, shft, 16, sop == 1);
+ val1 = lshift (cpu, val1, shft, 16, sop == 1, 1);
}
SET_ASTAT (ASTAT | astat);
STORE (DREG (dst0), (val1 << 16) | val0);
@@ -5294,7 +5302,7 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
STORE (DREG (dst0), ashiftrt (cpu, v, -shft, 32));
}
else
- STORE (DREG (dst0), lshift (cpu, v, shft, 32, sop == 1));
+ STORE (DREG (dst0), lshift (cpu, v, shft, 32, sop == 1, 1));
}
else if (sop == 3 && sopcde == 2)
{
@@ -5330,9 +5338,9 @@ decode_dsp32shift_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
}
else
{
- val0 = lshift (cpu, val0, shft, 16, 0);
+ val0 = lshift (cpu, val0, shft, 16, 0, 0);
astat = ASTAT;
- val1 = lshift (cpu, val1, shft, 16, 0);
+ val1 = lshift (cpu, val1, shft, 16, 0, 0);
}
SET_ASTAT (ASTAT | astat);
STORE (DREG (dst0), (val1 << 16) | val0);
@@ -5702,7 +5710,7 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
dst0, (HLs & 2) ? 'H' : 'L',
src1, (HLs & 1) ? 'H' : 'L', newimmag);
if (newimmag > 16)
- result = lshift (cpu, in, 16 - (newimmag & 0xF), 16, 0);
+ result = lshift (cpu, in, 16 - (newimmag & 0xF), 16, 0, 1);
else
result = ashiftrt (cpu, in, newimmag, 16);
}
@@ -5711,14 +5719,14 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
TRACE_INSN (cpu, "R%i.%c = R%i.%c << %i (S);",
dst0, (HLs & 2) ? 'H' : 'L',
src1, (HLs & 1) ? 'H' : 'L', immag);
- result = lshift (cpu, in, immag, 16, 1);
+ result = lshift (cpu, in, immag, 16, 1, 1);
}
else if (sop == 1 && bit8)
{
TRACE_INSN (cpu, "R%i.%c = R%i.%c >>> %i (S);",
dst0, (HLs & 2) ? 'H' : 'L',
src1, (HLs & 1) ? 'H' : 'L', immag);
- result = lshift (cpu, in, immag, 16, 1);
+ result = lshift (cpu, in, immag, 16, 1, 1);
}
else if (sop == 2 && bit8)
{
@@ -5732,7 +5740,7 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
TRACE_INSN (cpu, "R%i.%c = R%i.%c << %i;",
dst0, (HLs & 2) ? 'H' : 'L',
src1, (HLs & 1) ? 'H' : 'L', immag);
- result = lshift (cpu, in, immag, 16, 0);
+ result = lshift (cpu, in, immag, 16, 0, 1);
}
else
illegal_instruction (cpu);
@@ -5820,9 +5828,9 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
TRACE_INSN (cpu, "R%i = R%i << %i (V,S);", dst0, src1, count);
if (count >= 0)
{
- val0 = lshift (cpu, val0, count, 16, 1);
+ val0 = lshift (cpu, val0, count, 16, 1, 1);
astat = ASTAT;
- val1 = lshift (cpu, val1, count, 16, 1);
+ val1 = lshift (cpu, val1, count, 16, 1, 1);
}
else
{
@@ -5857,9 +5865,9 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
bu32 astat;
TRACE_INSN (cpu, "R%i = R%i << %i (V);", dst0, src1, count);
- val0 = lshift (cpu, val0, count, 16, 0);
+ val0 = lshift (cpu, val0, count, 16, 0, 1);
astat = ASTAT;
- val1 = lshift (cpu, val1, count, 16, 0);
+ val1 = lshift (cpu, val1, count, 16, 0, 1);
SET_ASTAT (ASTAT | astat);
STORE (DREG (dst0), val0 | (val1 << 16));
@@ -5876,9 +5884,9 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
if (count & 0x10)
{
- val0 = lshift (cpu, val0, 16 - (count & 0xF), 16, 0);
+ val0 = lshift (cpu, val0, 16 - (count & 0xF), 16, 0, 1);
astat = ASTAT;
- val1 = lshift (cpu, val1, 16 - (count & 0xF), 16, 0);
+ val1 = lshift (cpu, val1, 16 - (count & 0xF), 16, 0, 1);
}
else
{
@@ -5896,7 +5904,7 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
int count = imm6 (immag);
TRACE_INSN (cpu, "R%i = R%i << %i (S);", dst0, src1, count);
- STORE (DREG (dst0), lshift (cpu, DREG (src1), count, 32, 1));
+ STORE (DREG (dst0), lshift (cpu, DREG (src1), count, 32, 1, 1));
}
else if (sop == 2 && sopcde == 2)
{
@@ -5905,7 +5913,7 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
TRACE_INSN (cpu, "R%i = R%i >> %i;", dst0, src1, count);
if (count < 0)
- STORE (DREG (dst0), lshift (cpu, DREG (src1), -count, 32, 0));
+ STORE (DREG (dst0), lshift (cpu, DREG (src1), -count, 32, 0, 1));
else
STORE (DREG (dst0), lshiftrt (cpu, DREG (src1), count, 32));
}
@@ -5931,7 +5939,7 @@ decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
TRACE_INSN (cpu, "R%i = R%i >>> %i;", dst0, src1, count);
if (count < 0)
- STORE (DREG (dst0), lshift (cpu, DREG (src1), -count, 32, 0));
+ STORE (DREG (dst0), lshift (cpu, DREG (src1), -count, 32, 0, 1));
else
STORE (DREG (dst0), ashiftrt (cpu, DREG (src1), count, 32));
}
--
1.7.8.5
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] sim: bfin: add tests for new shift behavior
2012-03-19 5:05 [PATCH] sim: bfin: fix corner case Logical shift issues Mike Frysinger
@ 2012-03-19 5:18 ` Mike Frysinger
2012-03-19 5:26 ` Mike Frysinger
1 sibling, 0 replies; 3+ messages in thread
From: Mike Frysinger @ 2012-03-19 5:18 UTC (permalink / raw)
To: gdb-patches; +Cc: Robin Getz
[-- Attachment #1: Type: Text/Plain, Size: 5124 bytes --]
and of course, need tests to make sure new behavior works
-mike
2012-03-19 Robin Getz <robin.getz@analog.com>
* random_0014.S, random_0015.S, random_0016.S: New tests for shifts.
diff --git a/sim/testsuite/sim/bfin/random_0014.S b/sim/testsuite/sim/bfin/random_0014.S
new file mode 100644
index 0000000..c77b305
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0014.S
@@ -0,0 +1,82 @@
+# Test a few corner cases with various shift insns
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+ start
+
+ dmm32 ASTAT, (0x38404290 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN);
+ dmm32 A0.w, 0xf53d356e;
+ dmm32 A0.x, 0xffffffff;
+ imm32 R5, 0xaa156b54;
+ A0 = ASHIFT A0 BY R5.L;
+ checkreg A0.w, 0x56e00000;
+ checkreg A0.x, 0xffffffd3;
+ checkreg ASTAT, (0x38404290 | _VS | _V | _AC1 | _AC0 | _V_COPY | _AC0_COPY | _AN);
+
+ dmm32 ASTAT, (0x28e00410 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY);
+ dmm32 A0.w, 0x1dfd2a85;
+ dmm32 A0.x, 0xffffffbe;
+ imm32 R2, 0x4b7cf707;
+ A0 = LSHIFT A0 BY R2.L;
+ checkreg A0.w, 0xfe954280;
+ checkreg A0.x, 0x0000000e;
+ checkreg ASTAT, (0x28e00410 | _VS | _V | _AV1S | _AV1 | _AC1 | _V_COPY);
+
+ dmm32 ASTAT, (0x60404e00 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
+ dmm32 A1.w, 0xd4aa6e10;
+ dmm32 A1.x, 0xffffffff;
+ imm32 R4, 0xb4bb3054;
+ A1 = ASHIFT A1 BY R4.L;
+ checkreg A1.w, 0xe1000000;
+ checkreg A1.x, 0xffffffa6;
+ checkreg ASTAT, (0x60404e00 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
+
+ dmm32 ASTAT, (0x00608810 | _V | _AV1S | _AV0S | _V_COPY | _AC0_COPY | _AN);
+ dmm32 A1.w, 0x0dbadb4f;
+ dmm32 A1.x, 0x00000035;
+ imm32 R3, 0x3cc3f7db;
+ A1 = LSHIFT A1 BY R3.L;
+ checkreg A1.w, 0x78000000;
+ checkreg A1.x, 0xffffffda;
+ checkreg ASTAT, (0x00608810 | _V | _AV1S | _AV0S | _V_COPY | _AC0_COPY | _AN);
+
+ dmm32 ASTAT, (0x14900e10 | _VS | _AC0 | _CC | _AC0_COPY);
+ imm32 R0, 0x6286ee56;
+ imm32 R7, 0x5cd969c5;
+ R0 = ASHIFT R0 BY R7.L;
+ checkreg R0, 0x50ddcac0;
+ checkreg ASTAT, (0x14900e10 | _VS | _V | _AC0 | _CC | _V_COPY | _AC0_COPY);
+
+ dmm32 ASTAT, (0x28904a90 | _VS | _V | _AV0S | _V_COPY | _AZ);
+ imm32 R0, 0x00000000;
+ imm32 R5, 0x00008000;
+ imm32 R6, 0x03488f9a;
+ R0.L = ASHIFT R5.L BY R6.L;
+ checkreg ASTAT, (0x28904a90 | _VS | _V | _AV0S | _V_COPY | _AZ);
+
+ dmm32 ASTAT, (0x3c10c890 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _AC0_COPY);
+ imm32 R1, 0x29162006;
+ imm32 R3, 0xffff0345;
+ imm32 R4, 0x8ff5e6bb;
+ R1.H = ASHIFT R4.H BY R3.L;
+ checkreg R1, 0xfea02006;
+ checkreg ASTAT, (0x3c10c890 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _V_COPY | _AC0_COPY | _AN);
+
+ dmm32 ASTAT, (0x78600e00 | _VS | _AV1S | _AV0S | _AC0 | _AQ | _CC);
+ imm32 R0, 0xd5b1804d;
+ imm32 R1, 0x522c817d;
+ imm32 R5, 0xfca6f990;
+ R1.H = ASHIFT R5.H BY R0.L;
+ checkreg R1, 0xc000817d;
+ checkreg ASTAT, (0x78600e00 | _VS | _V | _AV1S | _AV0S | _AC0 | _AQ | _CC | _V_COPY | _AN);
+
+ dmm32 ASTAT, (0x64b04890 | _VS | _V | _AV0S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AN);
+ imm32 R4, 0x80000000;
+ imm32 R6, 0x4e840a3e;
+ imm32 R7, 0x20102e48;
+ R6.L = ASHIFT R4.H BY R7.L;
+ checkreg R6, 0x4e840000;
+ checkreg ASTAT, (0x64b04890 | _VS | _V | _AV0S | _AV0 | _AC1 | _AQ | _CC | _V_COPY | _AC0_COPY | _AZ);
+
+ pass
diff --git a/sim/testsuite/sim/bfin/random_0015.S b/sim/testsuite/sim/bfin/random_0015.S
new file mode 100644
index 0000000..60d6317
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0015.S
@@ -0,0 +1,25 @@
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+ start
+
+ dmm32 ASTAT, (0x5c70c410 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY | _AN);
+ dmm32 A1.w, 0xb7cc6ddd;
+ dmm32 A1.x, 0x00000004;
+ imm32 R3, 0x3f225ae3;
+ A1 = ASHIFT A1 BY R3.L;
+ checkreg A1.w, 0x00000025;
+ checkreg A1.x, 0x00000000;
+ checkreg ASTAT, (0x5c70c410 | _VS | _V | _AV0S | _AV0 | _AC1 | _V_COPY);
+
+ dmm32 ASTAT, (0x4810ca80 | _AV1S | _AV1 | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY | _AN);
+ dmm32 A1.w, 0x7396e11c;
+ dmm32 A1.x, 0xffffffba;
+ imm32 R3, 0x6e5f9f48;
+ A1 = ASHIFT A1 BY R3.L;
+ checkreg A1.w, 0x96e11c00;
+ checkreg A1.x, 0x00000073;
+ checkreg ASTAT, (0x4810ca80 | _AV1S | _AV0S | _AV0 | _AC1 | _AC0 | _V_COPY);
+
+ pass
diff --git a/sim/testsuite/sim/bfin/random_0016.S b/sim/testsuite/sim/bfin/random_0016.S
new file mode 100644
index 0000000..0b45074
--- /dev/null
+++ b/sim/testsuite/sim/bfin/random_0016.S
@@ -0,0 +1,26 @@
+# Test LSHIFT values and ASTAT flags
+# mach: bfin
+#include "test.h"
+.include "testutils.inc"
+
+ start
+
+ dmm32 ASTAT, (0x7ce00000 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY | _AN);
+ dmm32 A0.w, 0xe1a3909e;
+ dmm32 A0.x, 0xffffffff;
+ imm32 R2, 0x214a26f6;
+ A0 = LSHIFT A0 BY R2.L;
+ checkreg A0.w, 0x3ff868e4;
+ checkreg A0.x, 0x00000000;
+ checkreg ASTAT, (0x7ce00000 | _VS | _V | _AV0S | _AQ | _CC | _V_COPY);
+
+ dmm32 ASTAT, (0x64008a00 | _AV1 | _AV0S | _AV0 | _AC0 | _AQ | _CC | _AN);
+ dmm32 A0.w, 0x72af1593;
+ dmm32 A0.x, 0xfffffffd;
+ imm32 R2, 0x6505b40c;
+ A0 = LSHIFT A0 BY R2.L;
+ checkreg A0.w, 0xf1593000;
+ checkreg A0.x, 0x0000002a;
+ checkreg ASTAT, (0x64008a00 | _AV1 | _AV0S | _AC0 | _AQ | _CC);
+
+ pass
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^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] sim: bfin: add tests for new shift behavior
2012-03-19 5:05 [PATCH] sim: bfin: fix corner case Logical shift issues Mike Frysinger
2012-03-19 5:18 ` [PATCH] sim: bfin: add tests for new shift behavior Mike Frysinger
@ 2012-03-19 5:26 ` Mike Frysinger
1 sibling, 0 replies; 3+ messages in thread
From: Mike Frysinger @ 2012-03-19 5:26 UTC (permalink / raw)
To: gdb-patches; +Cc: Stuart Henderson
[-- Attachment #1: Type: Text/Plain, Size: 681 bytes --]
and another test for this behavior
-mike
2012-03-19 Stuart Henderson <stuart.henderson@analog.com>
* c_dsp32shiftim_amix.s: Check edge cases in shift behavior.
--- a/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s
+++ b/sim/testsuite/sim/bfin/c_dsp32shiftim_amix.s
@@ -114,6 +114,13 @@ R7 = R2 << 5 (S); /* r7 = 0x80000000 */
CHECKREG r6, 0x80000000;
CHECKREG r7, 0x80000000;
+imm32 r0, 0xFFFFFFF4;
+imm32 r2, 0xFFF00001;
+R6 = R0 << 31 (S); /* r6 = 0x80000000 */
+R7 = R2 << 31 (S); /* r7 = 0x80000000 */
+CHECKREG r6, 0x80000000;
+CHECKREG r7, 0x80000000;
+
// Ashift : NEGATIVE data, count (-)=right (half reg) Working ok
imm32 r0, 0x80f080f0;
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^ permalink raw reply [flat|nested] 3+ messages in thread
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2012-03-19 5:05 [PATCH] sim: bfin: fix corner case Logical shift issues Mike Frysinger
2012-03-19 5:18 ` [PATCH] sim: bfin: add tests for new shift behavior Mike Frysinger
2012-03-19 5:26 ` Mike Frysinger
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