Re: [RFA 7/8] New port: TI C6x: test case fixes

[Mark Kettenis <mark.kettenis@xs4all.nl>]

> Date: Tue, 09 Aug 2011 23:25:06 +0800
> From: Yao Qi <yao@codesourcery.com>
> 
> On 08/09/2011 11:15 PM, Mark Kettenis wrote:
> > Why depend on this NOMMU-magic?  Just install the signal handler for
> > bth SIGSEGV and SIGILL, try a store to (or perhaps a read from)
> > address 0, and then fall through to executing an illegal instruction.
> 
> Because I want to reduce the scope of using invalid instruction.  We
> only need to know the invalid instruction for HAS_NOMMU arch, and emit
> error if we forget to define an invalid instruction for a new NOMMU
> port.  Do it make sense?

I don't really think that's an issue.  If the test is run on an
mmu-less machine for which no illegal instruction is defined, the test
will fail.  That should prompt someone to look at the test and add the
missing instruction.

I really just want to avoid the #ifdef maze you're creating which
makes the code more complicated and the test less generic.  I think
you're too much focussed on reducing the number of FAILs for your
particular target to zero instead of improving the tests such that
they become more generally useful.  For example:

> diff --git a/gdb/testsuite/gdb.base/savedregs.exp b/gdb/testsuite/gdb.base/savedregs.exp
> index eeee0ff..4408137 100644
> --- a/gdb/testsuite/gdb.base/savedregs.exp
> +++ b/gdb/testsuite/gdb.base/savedregs.exp
> @@ -84,6 +84,14 @@ proc process_saved_regs { current inner outer } {
>  		# Sigtramp frames don't yet print <signal trampoline>.
>  		set pat "Stack frame at .* Saved registers:.*"
>  	    }
> +	    thrower {
> +		if { [istarget tic6x-*-*] } {
> +		    # On tic6x, there is no register saved in function thrower.
> +		    set pat "Stack frame at .* in $func .*"
> +		} else {
> +		    set pat "Stack frame at .* in $func .* Saved registers:.*"
> +		}

Why are you special-casing tic6x here?  Is the architecture really
that special that there are no saved registers?  I suspect it isn't
and that this can happen on other architectures as well, depending on
how much optimization the compiler is doing.