From: Daniel Jacobowitz <drow@false.org>
To: Ulrich Weigand <uweigand@de.ibm.com>
Cc: gdb-patches@sourceware.org
Subject: Re: [rfc][3/3] gdbserver bi-arch support: fix s390x partial register access
Date: Tue, 29 Jan 2008 20:36:00 -0000 [thread overview]
Message-ID: <20080129202746.GB15063@caradoc.them.org> (raw)
In-Reply-To: <200801211746.m0LHkQCl002914@d12av02.megacenter.de.ibm.com>
On Mon, Jan 21, 2008 at 06:46:26PM +0100, Ulrich Weigand wrote:
> The second problem is that when *setting* a partial register value, current
> code always pads the remainder of the register with zero. This is a problem
> with the PSW mask register on s390x, where one of the bits in the second
> half needs to be and remain set; otherwise the PSW is invalid and the
> inferior crashes.
>
> The patch fixes this by changing usr_store_inferior_registers by using a
> read-modify-write cycle when partially updating a register so that the
> bits in the part of the register that is not changed keep their old
> values.
What do you think about passing data to the low target in this case?
For MIPS the right bits will be value-dependent - registers must be
sign extended.
--
Daniel Jacobowitz
CodeSourcery
next prev parent reply other threads:[~2008-01-29 20:28 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2008-01-21 17:46 Ulrich Weigand
2008-01-29 20:36 ` Daniel Jacobowitz [this message]
2008-01-29 23:50 ` Ulrich Weigand
2008-02-26 8:15 ` Daniel Jacobowitz
2008-02-27 12:27 ` Ulrich Weigand
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