From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8220 invoked by alias); 29 Jan 2008 20:28:08 -0000 Received: (qmail 8209 invoked by uid 22791); 29 Jan 2008 20:28:08 -0000 X-Spam-Check-By: sourceware.org Received: from NaN.false.org (HELO nan.false.org) (208.75.86.248) by sourceware.org (qpsmtpd/0.31) with ESMTP; Tue, 29 Jan 2008 20:27:48 +0000 Received: from nan.false.org (localhost [127.0.0.1]) by nan.false.org (Postfix) with ESMTP id 2BE0D98151; Tue, 29 Jan 2008 20:27:47 +0000 (GMT) Received: from caradoc.them.org (22.svnf5.xdsl.nauticom.net [209.195.183.55]) by nan.false.org (Postfix) with ESMTP id 15F2A9811F; Tue, 29 Jan 2008 20:27:47 +0000 (GMT) Received: from drow by caradoc.them.org with local (Exim 4.68) (envelope-from ) id 1JJx3a-00046E-6f; Tue, 29 Jan 2008 15:27:46 -0500 Date: Tue, 29 Jan 2008 20:36:00 -0000 From: Daniel Jacobowitz To: Ulrich Weigand Cc: gdb-patches@sourceware.org Subject: Re: [rfc][3/3] gdbserver bi-arch support: fix s390x partial register access Message-ID: <20080129202746.GB15063@caradoc.them.org> Mail-Followup-To: Ulrich Weigand , gdb-patches@sourceware.org References: <200801211746.m0LHkQCl002914@d12av02.megacenter.de.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200801211746.m0LHkQCl002914@d12av02.megacenter.de.ibm.com> User-Agent: Mutt/1.5.17 (2007-12-11) X-IsSubscribed: yes Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org X-SW-Source: 2008-01/txt/msg00722.txt.bz2 On Mon, Jan 21, 2008 at 06:46:26PM +0100, Ulrich Weigand wrote: > The second problem is that when *setting* a partial register value, current > code always pads the remainder of the register with zero. This is a problem > with the PSW mask register on s390x, where one of the bits in the second > half needs to be and remain set; otherwise the PSW is invalid and the > inferior crashes. > > The patch fixes this by changing usr_store_inferior_registers by using a > read-modify-write cycle when partially updating a register so that the > bits in the part of the register that is not changed keep their old > values. What do you think about passing data to the low target in this case? For MIPS the right bits will be value-dependent - registers must be sign extended. -- Daniel Jacobowitz CodeSourcery