[commit] Fix altivec-regs.exp register format

[commit] Fix altivec-regs.exp register format

[Ulrich Weigand]

Hello,

the output format for AltiVec registers has changed once again;
this patch adapts the altivec-regs.exp test case accordingly.

Committed to mainline.

Bye,
Ulrich


ChangeLog:

	* gdb.arch/altivec-regs.exp (decimal_vector): Adjust for output
	format changes.

diff -urNp gdb-orig/gdb/testsuite/gdb.arch/altivec-regs.exp gdb-head/gdb/testsuite/gdb.arch/altivec-regs.exp
--- gdb-orig/gdb/testsuite/gdb.arch/altivec-regs.exp	2007-10-21 14:19:13.724733000 +0200
+++ gdb-head/gdb/testsuite/gdb.arch/altivec-regs.exp	2007-10-21 14:20:25.274332721 +0200
@@ -124,9 +124,9 @@ gdb_test "info reg vscr" "vscr.*0x1\t1" 
 # the way gdb works.
 
 if {$endianness == "big"} {
-     set decimal_vector ".uint128 = 0x00000001000000010000000100000001, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0 '.0', 0 '.0', 0 '.0', 1 '.001', 0 '.0', 0 '.0', 0 '.0', 1 '.001', 0 '.0', 0 '.0', 0 '.0', 1 '.001', 0 '.0', 0 '.0', 0 '.0', 1 '.001'.."
+     set decimal_vector ".uint128 = 0x00000001000000010000000100000001, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .0, 1, 0, 1, 0, 1, 0, 1., v16_int8 = .0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1.."
 } else {
-     set decimal_vector ".uint128 = 0x00000001000000010000000100000001, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1 '.001', 0 '.0', 0 '.0', 0 '.0', 1 '.001', 0 '.0', 0 '.0', 0 '.0', 1 '.001', 0 '.0', 0 '.0', 0 '.0', 1 '.001', 0 '.0', 0 '.0'.."
+     set decimal_vector ".uint128 = 0x00000001000000010000000100000001, v4_float = .1.*e-45, 1.*e-45, 1.*e-45, 1.*e-45., v4_int32 = .1, 1, 1, 1., v8_int16 = .1, 0, 1, 0, 1, 0, 1, 0., v16_int8 = .1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0.."
 }
 
 for {set i 0} {$i < 32} {incr i 1} {
-- 
  Dr. Ulrich Weigand
  GNU Toolchain for Linux on System z and Cell BE
  Ulrich.Weigand@de.ibm.com