From: Richard Earnshaw <rearnsha@arm.com>
To: Daniel Jacobowitz <drow@false.org>
Cc: Richard Earnshaw <rearnsha@arm.com>, gdb-patches@sources.redhat.com
Subject: Re: [rfa/arm] Handle bx and blx
Date: Mon, 08 Mar 2004 14:19:00 -0000 [thread overview]
Message-ID: <200403081419.i28EJTH10164@pc960.cambridge.arm.com> (raw)
Message-ID: <20040308141900.SYiCojaEqZzRaDyVmoEa31_iT_NKV1URqeH43FdixUY@z> (raw)
In-Reply-To: Your message of "Mon, 08 Mar 2004 09:09:49 EST." <20040308140948.GA14686@nevyn.them.org>
> On Mon, Mar 08, 2004 at 10:17:53AM +0000, Richard Earnshaw wrote:
> > > On Wed, Mar 03, 2004 at 04:01:55PM +0000, Richard Earnshaw wrote:
> > > > > The software single-step implementation in GDB doesn't know either BX or
> > > > > BLX. This results in losing control of the inferior when we single-step
> > > > > over them. I based this on the ARM ARM, so I'm pretty sure I've got the
> > > > > numbers correct.
> > > > >
> > > > > OK to check in?
> > > > >
> > > > > --
> > > > > Daniel Jacobowitz
> > > > > MontaVista Software Debian GNU/Linux Developer
> > > > >
> > > > > 2004-02-28 Daniel Jacobowitz <drow@mvista.com>
> > > > >
> > > > > * arm-tdep.c (thumb_get_next_pc): Handle BX.
> > > > > (arm_get_next_pc): Handle BX and BLX.
> > > >
> > > > Yikes! Yes, this is OK. However, Thumb has BLX (2 variants) as well.
> > >
> > > Right you are. I've checked in the above; if I'm reading
> > > thumb_get_next_pc and the ARM correctly, then the below is all I need
> > > for BLX. The first form is already handled since we don't check H.
> > > The second form can be handled identically to BX by relaxing a test.
> > >
> > > OK?
> > >
> > > --
> > > Daniel Jacobowitz
> > > MontaVista Software Debian GNU/Linux Developer
> > >
> > > 2004-03-07 Daniel Jacobowitz <drow@mvista.com>
> > >
> > > * arm-tdep.c (thumb_get_next_pc): Handle Thumb BLX.
> >
> > Very close, and possibly good enough for most purposes. But the ARM ARM
> > says that in the blx(1) case, the resulting address should be masked with
> > 0xfffffffc. That means that there are two theoretical encodings for each
> > target ARM-state instruction. I think you need to add a test for H=01 and
> > if so, to apply the mask to nextpc.
>
> Except it also says:
> Bit[0] for BLX If H == 01, then bit[0] of the instruction must
> be zero, or the instruction is UNDEFINED.
> The offset calculation method described
> in Usage above ensures that the offset
> calculated for a BLX instruction is a
> multiple of four, and that this
> restriction is obeyed.
>
> So I think the mask really isn't needed, or am I reading that wrong?
Ah, missed that bit. However, we could be starting with a pc value where
pc[1] != 0, so we still need the mask.
R.
next prev parent reply other threads:[~2004-03-08 14:19 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-02-28 18:35 Daniel Jacobowitz
2004-03-03 16:02 ` Richard Earnshaw
2004-03-07 20:15 ` Daniel Jacobowitz
2004-03-08 10:18 ` Richard Earnshaw
2004-03-19 0:09 ` Daniel Jacobowitz
2004-03-08 14:09 ` Daniel Jacobowitz
2004-03-19 0:09 ` Richard Earnshaw [this message]
2004-03-08 14:19 ` Richard Earnshaw
2004-03-08 14:25 ` Daniel Jacobowitz
2004-03-19 0:09 ` Richard Earnshaw
2004-03-08 14:28 ` Richard Earnshaw
2004-03-09 15:47 ` Daniel Jacobowitz
2004-03-19 0:09 ` Daniel Jacobowitz
2004-03-19 0:09 ` Daniel Jacobowitz
2004-03-19 0:09 ` Richard Earnshaw
2004-03-19 0:09 ` Daniel Jacobowitz
2004-03-19 0:09 ` Richard Earnshaw
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