[OBV PATCH] MPX documentation

[Walfred Tedeschi <walfred.tedeschi@intel.com>]

Fix some trademarks on MPX section.

2015-12-15  Walfred Tedeschi  <walfred.tedeschi@intel.com>

doc:
   	gdb.texinfo: (Intel(R) Memory Protection Extensions): Fix
	trademarks.

---
 gdb/doc/gdb.texinfo | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/gdb/doc/gdb.texinfo b/gdb/doc/gdb.texinfo
index fd7fc24..43e13bf 100644
--- a/gdb/doc/gdb.texinfo
+++ b/gdb/doc/gdb.texinfo
@@ -22013,15 +22013,16 @@ from functions.
 
 
 @subsubsection Intel(R) @dfn{Memory Protection Extensions} (MPX).
-@cindex Intel(R) Memory Protection Extensions (MPX).
-
-Memory Protection Extension (MPX) adds the bound registers @samp{BND0}
-@footnote{The register named with capital letters represent the architecture
-registers.} through @samp{BND3}.  Bound registers store a pair of 64-bit values
-which are the lower bound and upper bound.  Bounds are effective addresses or
-memory locations.  The upper bounds are architecturally represented in 1's
-complement form.  A bound having lower bound = 0, and upper bound = 0
-(1's complement of all bits set) will allow access to the entire address space.
+@cindex Intel(R) Memory Protection Extensions (Intel(R) MPX).
+
+Intel(R) Memory Protection Extension (Intel(R) MPX) adds the bound
+registers @samp{BND0} @footnote{The register named with capital
+letters represent the architecture registers.} through @samp{BND3}.
+Bound registers store a pair of 64-bit values which are the lower bound
+and upper bound.  Bounds are effective addresses or memory locations.
+The upper bounds are architecturally represented in 1's complement form.
+A bound having lower bound = 0, and upper bound = 0 (1's complement of
+all bits set) will allow access to the entire address space.
 
 @samp{BND0} through @samp{BND3} are represented in @value{GDBN} as @samp{bnd0raw}
 through @samp{bnd3raw}.  Pseudo registers @samp{bnd0} through @samp{bnd3}
-- 
2.1.4