[PATCH 0/3] Handle gnu vector in inferior call on AArch64

[PATCH 0/3] Handle gnu vector in inferior call on AArch64

[Yao Qi]

The patch set teaches GDB to understand GNU vector in AArch64 calling
convention.  Patch #1 is mainly about GNU vector support, and patch #2
is about handling homogeneous floating aggregate and homogeneous vector
aggregate.  We didn't have a specific test case for SIMD types used in
both ARM and AArch64, so patch #3 adds a new test case.  Without
patch #2, some tests in patch #3 will fail.

*** BLURB HERE ***

Yao Qi (3):
  [AArch64] Support gnu vector in inferior call
  [AArch64] Handle HFA and HVA together
  New test gdb.arch/arm-neon.exp

 gdb/aarch64-tdep.c                  |  76 +++++++++++++++++++++------
 gdb/testsuite/gdb.arch/arm-neon.c   | 102 ++++++++++++++++++++++++++++++++++++
 gdb/testsuite/gdb.arch/arm-neon.exp |  62 ++++++++++++++++++++++
 3 files changed, 223 insertions(+), 17 deletions(-)
 create mode 100644 gdb/testsuite/gdb.arch/arm-neon.c
 create mode 100644 gdb/testsuite/gdb.arch/arm-neon.exp

-- 
1.9.1

[PATCH 2/3] [AArch64] Handle HFA and HVA together

[Yao Qi]

AArch64 AAPCS defined HFA (homogeneous floating-point aggregate)
and HVF (homogeneous short vector aggregate), bug GDB only handles the
former.  In the AAPCS doc, both types are treated exactly the same
in terms of alignment and passing locations (on registers or stack).
This patch is to extend is_hfa to handle both HFA and HVA.

gdb:

2015-11-20  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (is_hfa): Rename to ...
	(is_hfa_or_hva): ... this.  Handle vector type.  All callers
	updated.
	(aarch64_extract_return_value): Update debugging message.
	(aarch64_store_return_value): Likewise.
	(aarch64_return_in_memory): Update comments.
---
 gdb/aarch64-tdep.c | 37 ++++++++++++++++++++-----------------
 1 file changed, 20 insertions(+), 17 deletions(-)

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 175ed08..cdc1b93 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -921,11 +921,12 @@ aarch64_type_align (struct type *t)
     }
 }
 
-/* Return 1 if *TY is a homogeneous floating-point aggregate as
-   defined in the AAPCS64 ABI document; otherwise return 0.  */
+/* Return 1 if *TY is a homogeneous floating-point aggregate or
+   homogeneous short-vector aggregate as defined in the AAPCS64 ABI
+   document; otherwise return 0.  */
 
 static int
-is_hfa (struct type *ty)
+is_hfa_or_hva (struct type *ty)
 {
   switch (TYPE_CODE (ty))
     {
@@ -936,7 +937,10 @@ is_hfa (struct type *ty)
 	if (TYPE_VECTOR (ty))
 	  return 0;
 
-	if (TYPE_CODE (target_ty) == TYPE_CODE_FLT && TYPE_LENGTH (ty) <= 4)
+	if (TYPE_LENGTH (ty) <= 4 /* HFA or HVA has at most 4 members.  */
+	    && (TYPE_CODE (target_ty) == TYPE_CODE_FLT /* HFA */
+		|| (TYPE_CODE (target_ty) == TYPE_CODE_ARRAY /* HVA */
+		    && TYPE_VECTOR (target_ty))))
 	  return 1;
 	break;
       }
@@ -944,12 +948,15 @@ is_hfa (struct type *ty)
     case TYPE_CODE_UNION:
     case TYPE_CODE_STRUCT:
       {
+	/* HFA or HVA has at most four members.  */
 	if (TYPE_NFIELDS (ty) > 0 && TYPE_NFIELDS (ty) <= 4)
 	  {
 	    struct type *member0_type;
 
 	    member0_type = check_typedef (TYPE_FIELD_TYPE (ty, 0));
-	    if (TYPE_CODE (member0_type) == TYPE_CODE_FLT)
+	    if (TYPE_CODE (member0_type) == TYPE_CODE_FLT
+		|| (TYPE_CODE (member0_type) == TYPE_CODE_ARRAY
+		    && TYPE_VECTOR (member0_type)))
 	      {
 		int i;
 
@@ -1304,7 +1311,7 @@ aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 	case TYPE_CODE_STRUCT:
 	case TYPE_CODE_ARRAY:
 	case TYPE_CODE_UNION:
-	  if (is_hfa (arg_type))
+	  if (is_hfa_or_hva (arg_type))
 	    {
 	      int elements = TYPE_NFIELDS (arg_type);
 
@@ -1640,7 +1647,7 @@ aarch64_extract_return_value (struct type *type, struct regcache *regs,
       memcpy (valbuf, buf, len);
       valbuf += len;
     }
-  else if (is_hfa (type))
+  else if (is_hfa_or_hva (type))
     {
       int elements = TYPE_NFIELDS (type);
       struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
@@ -1654,7 +1661,7 @@ aarch64_extract_return_value (struct type *type, struct regcache *regs,
 
 	  if (aarch64_debug)
 	    {
-	      debug_printf ("read HFA return value element %d from %s\n",
+	      debug_printf ("read HFA or HVA return value element %d from %s\n",
 			    i + 1,
 			    gdbarch_register_name (gdbarch, regno));
 	    }
@@ -1705,14 +1712,10 @@ aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type)
 
   type = check_typedef (type);
 
-  /* In the AArch64 ABI, "integer" like aggregate types are returned
-     in registers.  For an aggregate type to be integer like, its size
-     must be less than or equal to 4 * X_REGISTER_SIZE.  */
-
-  if (is_hfa (type))
+  if (is_hfa_or_hva (type))
     {
-      /* PCS B.5 If the argument is a Named HFA, then the argument is
-         used unmodified.  */
+      /* v0-v7 are used to return values and one register is allocated
+	 for one member.  However, HFA or HVA has at most four members.  */
       return 0;
     }
 
@@ -1778,7 +1781,7 @@ aarch64_store_return_value (struct type *type, struct regcache *regs,
 	    }
 	}
     }
-  else if (is_hfa (type))
+  else if (is_hfa_or_hva (type))
     {
       int elements = TYPE_NFIELDS (type);
       struct type *member_type = check_typedef (TYPE_FIELD_TYPE (type, 0));
@@ -1792,7 +1795,7 @@ aarch64_store_return_value (struct type *type, struct regcache *regs,
 
 	  if (aarch64_debug)
 	    {
-	      debug_printf ("write HFA return value element %d to %s\n",
+	      debug_printf ("write HFA or HVA return value element %d to %s\n",
 			    i + 1,
 			    gdbarch_register_name (gdbarch, regno));
 	    }
-- 
1.9.1

[PATCH 3/3] New test gdb.arch/arm-neon.exp

[Yao Qi]

Both ARM and AArch64 have defined some SIMD data types in arm_neon.h,
but we don't have a test case for passing them and returning them in
inferior call.  This test also covers passing and returning
homogeneous short vector aggregate (defined by AArch64 ABI document)
in inferior call too.

gdb/testsuite:

	* gdb.arch/arm-neon.exp: New.
	* gdb.arch/arm-neon.c: New.
---
 gdb/testsuite/gdb.arch/arm-neon.c   | 102 ++++++++++++++++++++++++++++++++++++
 gdb/testsuite/gdb.arch/arm-neon.exp |  62 ++++++++++++++++++++++
 2 files changed, 164 insertions(+)
 create mode 100644 gdb/testsuite/gdb.arch/arm-neon.c
 create mode 100644 gdb/testsuite/gdb.arch/arm-neon.exp

diff --git a/gdb/testsuite/gdb.arch/arm-neon.c b/gdb/testsuite/gdb.arch/arm-neon.c
new file mode 100644
index 0000000..e1fdd34
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/arm-neon.c
@@ -0,0 +1,102 @@
+/* Copyright 2015 Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+#include <arm_neon.h>
+
+#define DEF_FUNC1(N, TYPE, VALUE...)	\
+  TYPE a##N = {VALUE};			\
+  TYPE vec_func##N(TYPE a)		\
+  { return a; }
+
+/* 64-bit vector.  */
+
+DEF_FUNC1(1, int8x8_t, -1, -2, 3, 4, 5, -6, 7, 8)
+DEF_FUNC1(2, int16x4_t, 0, 2, -4, 6)
+DEF_FUNC1(3, int32x2_t, -10, 12)
+DEF_FUNC1(4, uint8x8_t, 1, 2, 3, 4, 5, 6, 7, 8)
+DEF_FUNC1(5, uint16x4_t, 4, 3, 2, 1)
+DEF_FUNC1(6, uint32x2_t, 100, 200)
+DEF_FUNC1(7, float32x2_t, 1.0, 2.0)
+DEF_FUNC1(8, poly8x8_t, 8, 10, 12, 14, 15, 16, 1, 0)
+DEF_FUNC1(9, poly16x4_t, 32, 33, 34, 35)
+
+/* 128-bit vector.  */
+
+DEF_FUNC1(10, int8x16_t, -1, -2, 3, 4, 5, -6, 7, 8, 8, 10, 12, 14, 15, 16, 1, 0);
+DEF_FUNC1(11, int16x8_t, 4, 10, -13, -16, 18, 1, 2, 4);
+DEF_FUNC1(12, int32x4_t, 32, 33, -34, 35);
+DEF_FUNC1(13, uint8x16_t, 1, 2, 3, 4, 5, 6, 7, 8, 8, 10, 12, 14, 15, 16, 1, 0);
+DEF_FUNC1(14, uint16x8_t, 4, 10, 13, 16, 18, 1, 2, 4);
+DEF_FUNC1(15, uint32x4_t, 16, 18, 1, 2);
+DEF_FUNC1(16, float32x4_t, 2.0, 5.0, 4.0, 8.0);
+DEF_FUNC1(17, poly8x16_t, 8, 10, 12, 14, 15, 16, 1, 0, 8, 10, 12, 14, 15, 16, 1, 0);
+DEF_FUNC1(18, poly16x8_t, 8, 10, 12, 14, 15, 16, 1, 0);
+
+/* Homogeneous Short Vector Aggregate.  */
+
+struct hva1
+{
+  int8x8_t f1;
+  int8x8_t f2;
+  int8x8_t f3;
+};
+
+struct hva2
+{
+  int8x8_t f1;
+  int16x4_t f2;
+  int32x2_t f3;
+};
+
+struct hva3
+{
+  int8x8_t f1;
+  int8x8_t f2;
+  int8x8_t f3;
+  int8x8_t f4;
+  int16x4_t f5;
+  int32x2_t f6;
+};
+
+struct hva1 hva1 = {{-1, -2, 3, 4, 5, -6, 7, 8},
+		    {-1, -2, 3, 4, 5, -6, 7, 8},
+		    {-1, -2, 3, 4, 5, -6, 7, 8}};
+
+struct hva2 hva2 = {{-1, -2, 3, 4, 5, -6, 7, 8},
+		    {0, 2, -4, 6},
+		    {-10, 12}};
+
+struct hva3 hva3 = {{-1, -2, 3, 4, 5, -6, 7, 8},
+		    {-1, -2, 3, 4, 5, -6, 7, 8},
+		    {-1, -2, 3, 4, 5, -6, 7, 8},
+		    {-1, -2, 3, 4, 5, -6, 7, 8},
+		    {0, 2, -4, 6},
+		    {-10, 12}};
+
+#define DEF_FUNC2(N)			  \
+  struct hva##N hva_func##N(struct hva##N a) \
+  { return a; }
+
+DEF_FUNC2 (1)
+DEF_FUNC2 (2)
+DEF_FUNC2 (3)
+
+int
+main (void)
+{
+  return 0;
+}
diff --git a/gdb/testsuite/gdb.arch/arm-neon.exp b/gdb/testsuite/gdb.arch/arm-neon.exp
new file mode 100644
index 0000000..b64a90b
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/arm-neon.exp
@@ -0,0 +1,62 @@
+# Copyright 2015 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# This file is part of the gdb testsuite.
+
+if {![istarget "aarch64*-*-*"] && ![istarget "arm*-*-*"]} {
+    verbose "Skipping ${gdb_test_file_name}."
+    return
+}
+
+standard_testfile
+if { [prepare_for_testing ${testfile}.exp ${testfile} ${srcfile}] } {
+    unsupported "ARM NEON is not supported"
+    return -1
+}
+
+if ![runto_main] {
+    untested "could not run to main"
+    return -1
+}
+
+# Test passing vectors in function argument in the inferior call.
+
+for {set i 1} {$i <= 18} {incr i} {
+
+    set contents ""
+    set test "print a${i}"
+    gdb_test_multiple "p a${i}" $test {
+	-re " = (.*)\r\n$gdb_prompt $" {
+	    set contents $expect_out(1,string)
+	}
+    }
+    regsub -all "\{" $contents "\\\\\{" contents
+    gdb_test "p vec_func${i} \(a${i}\)" "= $contents"
+}
+
+# Test passing homogeneous vector aggregate in function argument
+# in the inferior call.
+
+for {set i 1} {$i <= 3} {incr i} {
+    set contents ""
+    set test "print hva${i}"
+    gdb_test_multiple "p hva${i}" $test {
+	-re " = (.*)\r\n$gdb_prompt $" {
+	    set contents $expect_out(1,string)
+	}
+    }
+    regsub -all "\{" $contents "\\\\\{" contents
+    gdb_test "p hva_func${i} \(hva${i}\)" "= $contents"
+}
-- 
1.9.1

[PATCH 1/3] [AArch64] Support gnu vector in inferior call

[Yao Qi]

As defined in AArch64 AAPCS, short vectors are passed through V
registers, and its maximum alignment is 16-byte.  This patch is
to reflect these rules in GDB.  This patch fixes some fails in
gdb.base/gnu_vector.exp.

gdb:

2015-11-20  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_type_align): For vector type, return
	its length, but with the maximum of 16 bytes.
	(is_hfa): Return zero for vector type.
	(aarch64_push_dummy_call): Handle short vectors.
	(aarch64_extract_return_value): Likewise.
	(aarch64_store_return_value): Likewise.
---
 gdb/aarch64-tdep.c | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index de85cb0..175ed08 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -894,6 +894,17 @@ aarch64_type_align (struct type *t)
       return TYPE_LENGTH (t);
 
     case TYPE_CODE_ARRAY:
+      if (TYPE_VECTOR (t))
+	{
+	  /* Use the natural alignment for vector types (the same for
+	     scalar type), but the maximum alignment is 128-bit.  */
+	  if (TYPE_LENGTH (t) > 16)
+	    return 16;
+	  else
+	    return TYPE_LENGTH (t);
+	}
+      else
+	return aarch64_type_align (TYPE_TARGET_TYPE (t));
     case TYPE_CODE_COMPLEX:
       return aarch64_type_align (TYPE_TARGET_TYPE (t));
 
@@ -921,6 +932,10 @@ is_hfa (struct type *ty)
     case TYPE_CODE_ARRAY:
       {
 	struct type *target_ty = TYPE_TARGET_TYPE (ty);
+
+	if (TYPE_VECTOR (ty))
+	  return 0;
+
 	if (TYPE_CODE (target_ty) == TYPE_CODE_FLT && TYPE_LENGTH (ty) <= 4)
 	  return 1;
 	break;
@@ -1318,6 +1333,12 @@ aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 		  pass_on_stack (&info, arg_type, arg);
 		}
 	    }
+	  else if (TYPE_CODE (arg_type) == TYPE_CODE_ARRAY
+		   && TYPE_VECTOR (arg_type) && (len == 16 || len == 8))
+	    {
+		  /* Short vector types are passed in V registers.  */
+		  pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);
+	    }
 	  else if (len > 16)
 	    {
 	      /* PCS B.7 Aggregates larger than 16 bytes are passed by
@@ -1643,6 +1664,15 @@ aarch64_extract_return_value (struct type *type, struct regcache *regs,
 	  valbuf += len;
 	}
     }
+  else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
+	   && (TYPE_LENGTH (type) == 16 || TYPE_LENGTH (type) == 8))
+    {
+      /* Short vector is returned in V register.  */
+      gdb_byte buf[V_REGISTER_SIZE];
+
+      regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf);
+      memcpy (valbuf, buf, TYPE_LENGTH (type));
+    }
   else
     {
       /* For a structure or union the behaviour is as if the value had
@@ -1772,6 +1802,15 @@ aarch64_store_return_value (struct type *type, struct regcache *regs,
 	  valbuf += len;
 	}
     }
+  else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
+	   && (TYPE_LENGTH (type) == 8 || TYPE_LENGTH (type) == 16))
+    {
+      /* Short vector.  */
+      gdb_byte buf[V_REGISTER_SIZE];
+
+      memcpy (buf, valbuf, TYPE_LENGTH (type));
+      regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf);
+    }
   else
     {
       /* For a structure or union the behaviour is as if the value had
-- 
1.9.1

Re: [PATCH 1/3] [AArch64] Support gnu vector in inferior call

[Pedro Alves]

On 11/20/2015 04:11 PM, Yao Qi wrote:

> +	  else if (TYPE_CODE (arg_type) == TYPE_CODE_ARRAY
> +		   && TYPE_VECTOR (arg_type) && (len == 16 || len == 8))
> +	    {
> +		  /* Short vector types are passed in V registers.  */
> +		  pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);

Indentation looks odd here.

I have nothing useful to say about the patch though.

Thanks,
Pedro Alves

Re: [PATCH 1/3] [AArch64] Support gnu vector in inferior call

[Yao Qi]

Pedro Alves <palves@redhat.com> writes:

>> +	  else if (TYPE_CODE (arg_type) == TYPE_CODE_ARRAY
>> +		   && TYPE_VECTOR (arg_type) && (len == 16 || len == 8))
>> +	    {
>> +		  /* Short vector types are passed in V registers.  */
>> +		  pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);
>
> Indentation looks odd here.

Ur, sorry.  Patch is updated.

-- 
Yao (齐尧)

From: Yao Qi <yao.qi@linaro.org>
Subject: [PATCH] [AArch64] Support gnu vector in inferior call

As defined in AArch64 AAPCS, short vectors are passed through V
registers, and its maximum alignment is 16-byte.  This patch is
to reflect these rules in GDB.  This patch fixes some fails in
gdb.base/gnu_vector.exp.

gdb:

2015-11-20  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_type_align): For vector type, return
	its length, but with the maximum of 16 bytes.
	(is_hfa): Return zero for vector type.
	(aarch64_push_dummy_call): Handle short vectors.
	(aarch64_extract_return_value): Likewise.
	(aarch64_store_return_value): Likewise.

diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index de85cb0..8ce0eaa 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -894,6 +894,17 @@ aarch64_type_align (struct type *t)
       return TYPE_LENGTH (t);
 
     case TYPE_CODE_ARRAY:
+      if (TYPE_VECTOR (t))
+	{
+	  /* Use the natural alignment for vector types (the same for
+	     scalar type), but the maximum alignment is 128-bit.  */
+	  if (TYPE_LENGTH (t) > 16)
+	    return 16;
+	  else
+	    return TYPE_LENGTH (t);
+	}
+      else
+	return aarch64_type_align (TYPE_TARGET_TYPE (t));
     case TYPE_CODE_COMPLEX:
       return aarch64_type_align (TYPE_TARGET_TYPE (t));
 
@@ -921,6 +932,10 @@ is_hfa (struct type *ty)
     case TYPE_CODE_ARRAY:
       {
 	struct type *target_ty = TYPE_TARGET_TYPE (ty);
+
+	if (TYPE_VECTOR (ty))
+	  return 0;
+
 	if (TYPE_CODE (target_ty) == TYPE_CODE_FLT && TYPE_LENGTH (ty) <= 4)
 	  return 1;
 	break;
@@ -1318,6 +1333,12 @@ aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 		  pass_on_stack (&info, arg_type, arg);
 		}
 	    }
+	  else if (TYPE_CODE (arg_type) == TYPE_CODE_ARRAY
+		   && TYPE_VECTOR (arg_type) && (len == 16 || len == 8))
+	    {
+	      /* Short vector types are passed in V registers.  */
+	      pass_in_v_or_stack (gdbarch, regcache, &info, arg_type, arg);
+	    }
 	  else if (len > 16)
 	    {
 	      /* PCS B.7 Aggregates larger than 16 bytes are passed by
@@ -1643,6 +1664,15 @@ aarch64_extract_return_value (struct type *type, struct regcache *regs,
 	  valbuf += len;
 	}
     }
+  else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
+	   && (TYPE_LENGTH (type) == 16 || TYPE_LENGTH (type) == 8))
+    {
+      /* Short vector is returned in V register.  */
+      gdb_byte buf[V_REGISTER_SIZE];
+
+      regcache_cooked_read (regs, AARCH64_V0_REGNUM, buf);
+      memcpy (valbuf, buf, TYPE_LENGTH (type));
+    }
   else
     {
       /* For a structure or union the behaviour is as if the value had
@@ -1772,6 +1802,15 @@ aarch64_store_return_value (struct type *type, struct regcache *regs,
 	  valbuf += len;
 	}
     }
+  else if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type)
+	   && (TYPE_LENGTH (type) == 8 || TYPE_LENGTH (type) == 16))
+    {
+      /* Short vector.  */
+      gdb_byte buf[V_REGISTER_SIZE];
+
+      memcpy (buf, valbuf, TYPE_LENGTH (type));
+      regcache_cooked_write (regs, AARCH64_V0_REGNUM, buf);
+    }
   else
     {
       /* For a structure or union the behaviour is as if the value had

Re: [PATCH 0/3] Handle gnu vector in inferior call on AArch64

[Yao Qi]

Yao Qi <qiyaoltc@gmail.com> writes:

> The patch set teaches GDB to understand GNU vector in AArch64 calling
> convention.  Patch #1 is mainly about GNU vector support, and patch #2
> is about handling homogeneous floating aggregate and homogeneous vector
> aggregate.  We didn't have a specific test case for SIMD types used in
> both ARM and AArch64, so patch #3 adds a new test case.  Without
> patch #2, some tests in patch #3 will fail.

Patches are pushed in.

-- 
Yao (齐尧)