From: Jiri Gaisler <jiri@gaisler.se>
To: gdb-patches@sourceware.org
Cc: Jiri Gaisler <jiri@gaisler.se>
Subject: [PATCH v2 12/22] sim/erc32: Use memory_iread() function for instruction fetching.
Date: Thu, 19 Feb 2015 22:32:00 -0000 [thread overview]
Message-ID: <1424385100-15397-13-git-send-email-jiri@gaisler.se> (raw)
In-Reply-To: <1424385100-15397-1-git-send-email-jiri@gaisler.se>
Use separate memory_iread() function for instruction fetching.
Speeds up execution and allows addition of an MMU at a later stage.
* erc32.c (memory_iread) New function to fetch instructions.
* interf.c (run_sim) Use memory_iread.
* sis.c (run_sim) As above.
---
sim/erc32/erc32.c | 24 ++++++++++++++++++++++++
sim/erc32/interf.c | 5 ++---
sim/erc32/sis.c | 8 ++------
sim/erc32/sis.h | 2 ++
4 files changed, 30 insertions(+), 9 deletions(-)
diff --git a/sim/erc32/erc32.c b/sim/erc32/erc32.c
index eac49f7..03b40dc 100644
--- a/sim/erc32/erc32.c
+++ b/sim/erc32/erc32.c
@@ -1566,6 +1566,30 @@ store_bytes (mem, waddr, data, sz, ws)
/* Memory emulation */
int
+memory_iread(addr, data, ws)
+ uint32 addr;
+ uint32 *data;
+ int32 *ws;
+{
+ uint32 asi;
+ if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
+ *data = *((uint32 *) & (ramb[addr & mem_rammask & ~3]));
+ *ws = mem_ramr_ws;
+ return (0);
+ } else if (addr < mem_romsz) {
+ *data = *((uint32 *) & (romb[addr & ~3]));
+ *ws = mem_romr_ws;
+ return (0);
+ }
+
+ printf("Memory exception at %x (illegal address)\n", addr);
+ if (sregs.psr & 0x080) asi = 9; else asi = 8;
+ set_sfsr(UIMP_ACC, addr, asi, 1);
+ *ws = MEM_EX_WS;
+ return (1);
+}
+
+int
memory_read(asi, addr, data, sz, ws)
int32 asi;
uint32 addr;
diff --git a/sim/erc32/interf.c b/sim/erc32/interf.c
index 3a72e7f..981aa11 100644
--- a/sim/erc32/interf.c
+++ b/sim/erc32/interf.c
@@ -94,9 +94,8 @@ run_sim(sregs, icount, dis)
if (sregs->pc == 0 || sregs->npc == 0)
printf ("bogus pc or npc\n");
#endif
- mexc = memory_read(sregs->asi, sregs->pc, &sregs->inst,
- 2, &sregs->hold);
-#if 1 /* DELETE ME! for debugging purposes only */
+ mexc = memory_iread(sregs->pc, &sregs->inst, &sregs->hold);
+#if 0 /* DELETE ME! for debugging purposes only */
if (sis_verbose > 2)
printf("pc %x, np %x, sp %x, fp %x, wm %x, cw %x, i %08x\n",
sregs->pc, sregs->npc,
diff --git a/sim/erc32/sis.c b/sim/erc32/sis.c
index 523d8aa..e109874 100644
--- a/sim/erc32/sis.c
+++ b/sim/erc32/sis.c
@@ -84,7 +84,7 @@ run_sim(sregs, icount, dis)
uint64 icount;
int dis;
{
- int irq, mexc, deb, asi;
+ int irq, mexc, deb;
sregs->starttime = get_time();
init_stdio();
@@ -93,11 +93,7 @@ run_sim(sregs, icount, dis)
irq = 0;
while (icount > 0) {
- if (sregs->psr & 0x080)
- asi = 9;
- else
- asi = 8;
- mexc = memory_read(asi, sregs->pc, &sregs->inst, 2, &sregs->hold);
+ mexc = memory_iread(sregs->pc, &sregs->inst, &sregs->hold);
sregs->icnt = 1;
if (sregs->annul) {
sregs->annul = 0;
diff --git a/sim/erc32/sis.h b/sim/erc32/sis.h
index ef5b149..fb733de 100644
--- a/sim/erc32/sis.h
+++ b/sim/erc32/sis.h
@@ -176,6 +176,7 @@ extern void sim_halt (void);
extern void exit_sim (void);
extern void init_stdio (void);
extern void restore_stdio (void);
+extern int memory_iread (uint32 addr, uint32 *data, int32 *ws);
extern int memory_read (int32 asi, uint32 addr, uint32 *data,
int32 sz, int32 *ws);
extern int memory_write (int32 asi, uint32 addr, uint32 *data,
@@ -186,6 +187,7 @@ extern int sis_memory_read (uint32 addr, char *data,
uint32 length);
/* func.c */
+extern struct pstate sregs;
extern void set_regi (struct pstate *sregs, int32 reg,
uint32 rval);
extern void get_regi (struct pstate *sregs, int32 reg, char *buf);
--
2.1.0
next prev parent reply other threads:[~2015-02-19 22:32 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-19 22:32 [PATCH v2 00/22] Update of the SPARC SIS simulator Jiri Gaisler
2015-02-19 22:32 ` [PATCH v2 01/22] sim/erc32: Disassembly in stand-alone mode did not work Jiri Gaisler
2015-02-22 4:10 ` Mike Frysinger
2015-02-19 22:32 ` [PATCH v2 20/22] sim/erc32: Updated documentation Jiri Gaisler
2015-02-19 22:32 ` [PATCH v2 16/22] sim/erc32: Use readline.h for readline types and functions Jiri Gaisler
2015-02-22 20:58 ` Mike Frysinger
2015-02-19 22:32 ` [PATCH v2 14/22] sim/erc32: Use gdb callback for UART I/O when linked with gdb Jiri Gaisler
2015-02-22 21:02 ` Mike Frysinger
2015-02-19 22:32 ` [PATCH v2 17/22] sim/erc32: Move local extern declarations into sis.h Jiri Gaisler
2015-02-22 20:59 ` Mike Frysinger
2015-02-19 22:32 ` [PATCH v2 11/22] sim/erc32: use SIM_AC_OPTION_HOSTENDIAN to probe for host endianess Jiri Gaisler
2015-02-22 20:52 ` Mike Frysinger
2015-02-19 22:32 ` [PATCH v2 19/22] sim/erc32: Add support for LEON2 processor emulation Jiri Gaisler
2015-02-22 21:06 ` Mike Frysinger
2015-02-19 22:32 ` [PATCH v2 02/22] sim/erc32: Corrected wrong CPU implementation and version ID in psr Jiri Gaisler
2015-02-22 4:15 ` Mike Frysinger
2015-02-19 22:32 ` [PATCH v2 21/22] sim/erc32: Add data watchpoint support Jiri Gaisler
2015-02-19 22:32 ` [PATCH v2 22/22] Add watchpoint support to gdb simulator interface Jiri Gaisler
2015-02-19 22:32 ` Jiri Gaisler [this message]
2015-02-22 20:54 ` [PATCH v2 12/22] sim/erc32: Use memory_iread() function for instruction fetching Mike Frysinger
2015-02-19 22:32 ` [PATCH v2 06/22] sim/erc32: Fix incorrect simulator performance report Jiri Gaisler
2015-02-22 4:29 ` Mike Frysinger
2015-02-19 22:32 ` [PATCH v2 05/22] sim/erc32: Remove unused defines in Makefile and switch off statistics Jiri Gaisler
2015-02-22 4:24 ` Mike Frysinger
2015-02-19 22:33 ` [PATCH v2 08/22] sim/erc32: Added -v command line switch for verbose output Jiri Gaisler
2015-02-22 4:34 ` Mike Frysinger
2015-02-19 22:33 ` [PATCH v2 09/22] sim/erc32: Removed type mismatch compiler warnings Jiri Gaisler
2015-02-22 4:43 ` Mike Frysinger
2015-02-19 22:33 ` [PATCH v2 13/22] sim/erc32: Fix a few " Jiri Gaisler
2015-02-22 20:56 ` Mike Frysinger
2015-02-19 22:33 ` [PATCH v2 18/22] sim/erc32: Add support for LEON3 processor emulation Jiri Gaisler
2015-02-19 22:33 ` [PATCH v2 03/22] sim/erc32: Perform pseudo-init if binary linked to non-zero address Jiri Gaisler
2015-02-22 4:17 ` Mike Frysinger
2015-02-19 22:33 ` [PATCH v2 15/22] sim/erc32: Access memory subsystem through struct memsys Jiri Gaisler
2015-02-22 21:01 ` Mike Frysinger
2015-02-19 22:33 ` [PATCH v2 10/22] sim/erc32: Switched emulated memory to host endian order Jiri Gaisler
2015-02-22 20:51 ` Mike Frysinger
2015-02-22 23:10 ` Jiri Gaisler
2015-02-23 19:39 ` Mike Frysinger
2015-02-19 22:33 ` [PATCH v2 04/22] sim/erc32: Use fenv.h for host FPU access Jiri Gaisler
2015-02-22 4:24 ` Mike Frysinger
2015-02-19 22:33 ` [PATCH v2 07/22] sim/erc32: File loading via command line did not work Jiri Gaisler
2015-02-22 4:32 ` Mike Frysinger
2015-02-21 19:29 ` [PATCH v2 00/22] Update of the SPARC SIS simulator Mike Frysinger
2015-02-21 20:26 ` Jiri Gaisler
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