From: Catalin Udma <catalin.udma@freescale.com>
To: <gdb-patches@sourceware.org>
Cc: Catalin Udma <catalin.udma@freescale.com>
Subject: [PATCH] aarch64/gdbserver: fix floating point registers display
Date: Tue, 12 Aug 2014 09:23:00 -0000 [thread overview]
Message-ID: <1407835166-827-1-git-send-email-catalin.udma@freescale.com> (raw)
When using aarch64 gdb with gdbserver, floating point registers are
not correctly displayed, as below:
(gdb) info registers fpsr fpcr
fpsr <unavailable>
fpcr <unavailable>
Also, the offset for floating point v0-v31 registers in gdbserver
is wrong because it is computed based on 32-bit size of CPSR register
as defined in the regformat/aarch64.dat file
To fix these problems, the missing fpsr and fpcr registers are added
when floating point registers are read/write and the aarch64.dat file
is updated to use the correct CPSR size of 64-bits accordingly to the
definition in aarch64-core.xml
gdb/
2014-08-12 Catalin Udma <catalin.udma@freescale.com>
* regformats/aarch64.dat (cpsr): Change to be 64bit.
gdb/gdbserver/
2014-08-12 Catalin Udma <catalin.udma@freescale.com>
* linux-aarch64-low.c (AARCH64_FPSR_REGNO): New define.
(AARCH64_FPCR_REGNO): Likewise.
(AARCH64_NUM_REGS): Update to include fpsr/fpcr registers.
(aarch64_fill_fpregset): Add missing fpsp/fpcr registers.
(aarch64_store_fpregset): Likewise.
---
gdb/gdbserver/linux-aarch64-low.c | 8 +++++++-
gdb/regformats/aarch64.dat | 2 +-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/gdb/gdbserver/linux-aarch64-low.c b/gdb/gdbserver/linux-aarch64-low.c
index 6066e15..3453b2e 100644
--- a/gdb/gdbserver/linux-aarch64-low.c
+++ b/gdb/gdbserver/linux-aarch64-low.c
@@ -46,8 +46,10 @@ extern const struct target_desc *tdesc_aarch64;
#define AARCH64_PC_REGNO 32
#define AARCH64_CPSR_REGNO 33
#define AARCH64_V0_REGNO 34
+#define AARCH64_FPSR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
+#define AARCH64_FPCR_REGNO (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 1)
-#define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM)
+#define AARCH64_NUM_REGS (AARCH64_V0_REGNO + AARCH64_V_REGS_NUM + 2)
static int
aarch64_regmap [] =
@@ -255,6 +257,8 @@ aarch64_fill_fpregset (struct regcache *regcache, void *buf)
for (i = 0; i < AARCH64_V_REGS_NUM; i++)
collect_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
+ collect_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
+ collect_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
}
static void
@@ -265,6 +269,8 @@ aarch64_store_fpregset (struct regcache *regcache, const void *buf)
for (i = 0; i < AARCH64_V_REGS_NUM; i++)
supply_register (regcache, AARCH64_V0_REGNO + i, ®set->vregs[i]);
+ supply_register (regcache, AARCH64_FPSR_REGNO, ®set->fpsr);
+ supply_register (regcache, AARCH64_FPCR_REGNO, ®set->fpcr);
}
/* Debugging of hardware breakpoint/watchpoint support. */
diff --git a/gdb/regformats/aarch64.dat b/gdb/regformats/aarch64.dat
index afe1028..0d32183 100644
--- a/gdb/regformats/aarch64.dat
+++ b/gdb/regformats/aarch64.dat
@@ -35,7 +35,7 @@ expedite:x29,sp,pc
64:x30
64:sp
64:pc
-32:cpsr
+64:cpsr
128:v0
128:v1
128:v2
--
1.7.8
next reply other threads:[~2014-08-12 9:23 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-08-12 9:23 Catalin Udma [this message]
2014-08-12 9:43 ` Richard Earnshaw
2014-08-12 10:29 ` Yao Qi
2014-08-13 12:24 ` Philippe Waroquiers
2014-08-13 12:43 ` catalin.udma
[not found] ` <53EB5C86.4030307@codesourcery.com>
2014-08-13 14:42 ` Richard Earnshaw
2014-08-20 17:36 ` Pedro Alves
2014-08-21 6:54 ` catalin.udma
2014-08-21 6:56 ` Andrew Pinski
2014-08-21 7:30 ` Yao Qi
2014-08-21 16:05 ` Pedro Alves
2014-10-01 9:51 ` Pedro Alves
2014-10-06 9:06 ` catalin.udma
2014-10-06 12:28 ` Pedro Alves
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