[patch v5 12/12] btrace, x86: disable on some processors

[markus.t.metzger@intel.com]

From: Markus Metzger <markus.t.metzger@intel.com>

LBR, BTM, or BTS records may have incorrect branch "from" information afer an
EIST transition, T-states, C1E, or Adaptive Thermal Throttling (AAJ122).

This results in sporadic test fails. Disable btrace on those processors.

2012-12-07 Markus Metzger <markus.t.metzger@intel.com>

	* common/linux-btrace.c (linux_supports_btrace): Add cpuid check.


---
 gdb/common/linux-btrace.c |   43 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 43 insertions(+), 0 deletions(-)

diff --git a/gdb/common/linux-btrace.c b/gdb/common/linux-btrace.c
index 2441816..c703dc2 100644
--- a/gdb/common/linux-btrace.c
+++ b/gdb/common/linux-btrace.c
@@ -247,7 +247,50 @@ perf_event_read_bts (struct btrace_target_info* tinfo, const uint8_t *begin,
 int
 linux_supports_btrace (void)
 {
+#if defined(__i386__) || defined(__x86_64__)
+  {
+    unsigned int cpuid, model, family;
+
+    __asm__ __volatile__ ("movl   $1, %%eax;"
+			  "cpuid;"
+			  : "=a" (cpuid)
+			  :: "%ebx", "%ecx", "%edx");
+
+    family = (cpuid >> 8) & 0xf;
+    model = (cpuid >> 4) & 0xf;
+
+    switch (family)
+      {
+      case 6:
+	model += (cpuid >> 12) & 0xf0;
+
+	switch (model)
+	  {
+	  case 26: /* Nehalem */
+	  case 30:
+	  case 46:
+	  case 37: /* Westmere */
+	  case 44:
+	  case 47:
+	  case 42: /* Sandy Bridge */
+	  case 45:
+	  case 58: /* Ivy Bridge */
+
+	    /* AAJ122: LBR, BTM, or BTS records may have incorrect branch
+	       "from" information afer an EIST transition, T-states, C1E, or
+	       Adaptive Thermal Throttling.  */
+	    return 0;
+	  }
+      }
+  }
+
   return 1;
+
+#else /* defined(__i386__) || defined(__x86_64__) */
+
+  return 0;
+
+#endif /* defined(__i386__) || defined(__x86_64__) */
 }
 
 /* See linux-btrace.h.  */
-- 
1.7.1