[patch] correct handling of lswx and mtfsfi instructions in ppc simulator

[Julien Ducourthial <jducourt@noos.fr>]

Hi,

When running a program (which works ok on PPC boards) in the simulator:
        * the lswx instruction generates exceptions where it should not,
        * the mtfsi instruction is not recognized at all.

After checking ppc-instructions :
        * it seems there are a few typos in the registers handling in
          lswx (using bytes or bits index instead of register numbers). 
        * the prefix of mtfsfi is 64 instead of 63 (from "Powerpc : The
          Programming Environment").

the patch below fixes both problems.

2001-12-09  Julien Ducourthial <jducourt@noos.fr>
	* ppc-instructions (lswx): do the register control with the
	register count. Initialize the right register in the loop.
	* (mtfsfi) : correct prefix for the instruction.

Index: ppc-instructions
===================================================================
RCS file: /cvs/src/src/sim/ppc/ppc-instructions,v
retrieving revision 1.3
diff -c -3 -r1.3 ppc-instructions
*** ppc-instructions	2000/10/24 16:16:43	1.3
--- ppc-instructions	2001/12/09 07:49:47
***************
*** 2275,2285 ****
  	r = RT - 1;
  	i = 32;
  	nr = (n + 3) / 4;
! 	if (((RT + n >= 32)
! 	     ? ((RA >= RT || RA < (RT + n) % 32)
! 	        || (RB >= RT || RB < (RT + n) % 32))
! 	     : ((RA >= RT && RA < RT + n)
! 	        || (RB >= RT && RB < RT + n)))
  	    || (RT == RA || RT == RB))
  	  program_interrupt(processor, cia,
  	                  illegal_instruction_program_interrupt);
--- 2275,2285 ----
  	r = RT - 1;
  	i = 32;
  	nr = (n + 3) / 4;
! 	if (((RT + nr >= 32)
! 	     ? ((RA >= RT || RA < (RT + nr) % 32)
! 	        || (RB >= RT || RB < (RT + nr) % 32))
! 	     : ((RA >= RT && RA < RT + nr)
! 	        || (RB >= RT && RB < RT + nr)))
  	    || (RT == RA || RT == RB))
  	  program_interrupt(processor, cia,
  	                  illegal_instruction_program_interrupt);
***************
*** 2288,2294 ****
  	while (n > 0) {
  	  if (i == 32) {
  	    r = (r + 1) % 32;
! 	    GPR(i) = 0;
  	  }
  	  GPR(r) |= INSERTED(MEM(unsigned, EA, 1), i, i+7);
  	  i = i + 8;
--- 2288,2294 ----
  	while (n > 0) {
  	  if (i == 32) {
  	    r = (r + 1) % 32;
! 	    GPR(r) = 0;
  	  }
  	  GPR(r) |= INSERTED(MEM(unsigned, EA, 1), i, i+7);
  	  i = i + 8;
***************
*** 4582,4588 ****
  	FPSCR_SET(BFA, 0); /* FPSCR_END fixes up FEX/VX */
  	FPSCR_END(0);
  
! 0.64,6.BF,9./,11./,16.U,20./,21.134,31.Rc:X:f::Move To FPSCR Field
Immediate
  	FPSCR_BEGIN;
  	FPSCR_SET(BF, U);
  	FPSCR_END(Rc);
--- 4582,4588 ----
  	FPSCR_SET(BFA, 0); /* FPSCR_END fixes up FEX/VX */
  	FPSCR_END(0);
  
! 0.63,6.BF,9./,11./,16.U,20./,21.134,31.Rc:X:f::Move To FPSCR Field
Immediate
  	FPSCR_BEGIN;
  	FPSCR_SET(BF, U);
  	FPSCR_END(Rc);