* [RFA] xtensa-tdep.c ARI fix
@ 2009-02-13 18:00 Pierre Muller
2009-02-13 18:58 ` Maxim Grigoriev
0 siblings, 1 reply; 3+ messages in thread
From: Pierre Muller @ 2009-02-13 18:00 UTC (permalink / raw)
To: gdb-patches, maxim2405
Current ARI
has one critical "hash" failure:
hash 1 Do not use ` #...', instead use `#...'
(some compilers only correctly parse a C preprocessor directive when `#' is
the first character on the line)
coming from xtensa-tdep.c
It appears that the offending line is
#define BSZ 32 /* Instruction buffer size. */
I could have removed the starting spaces and commit the change as obvious,
but there is already a macro defining the instruction buffer size
at line 1050:
#define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
So I propose here a patch getting rid of the BSZ macro
and using XTENSA_ISA_BSZ in place of BSZ
in call0_analyse_prologue function.
Maxim, is this OK?
2009-02-13 Pierre Muller <muller@ics.u-strasbg.fr>
* xtensa-tdep.c (call0_analyze_prologue): Delete BSZ macro.
Replace BSZ macro uses by XTENSA_ISA_BSZ macro.
Index: xtensa-tdep.c
===================================================================
RCS file: /cvs/src/src/gdb/xtensa-tdep.c,v
retrieving revision 1.30
diff -u -p -r1.30 xtensa-tdep.c
--- xtensa-tdep.c 3 Jan 2009 05:57:54 -0000 1.30
+++ xtensa-tdep.c 13 Feb 2009 16:44:55 -0000
@@ -2092,8 +2092,7 @@ call0_analyze_prologue (CORE_ADDR start,
CORE_ADDR ia; /* Current insn address in prologue. */
CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
CORE_ADDR bt; /* Current address at top+1 of insn
buffer.
*/
- #define BSZ 32 /* Instruction buffer size. */
- char ibuf[BSZ]; /* Instruction buffer for decoding prologue. */
+ char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue.
*/
xtensa_isa isa; /* libisa ISA handle. */
xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
xtensa_format ifmt; /* libisa instruction format. */
@@ -2153,7 +2152,7 @@ call0_analyze_prologue (CORE_ADDR start,
if (!xtensa_default_isa)
xtensa_default_isa = xtensa_isa_init (0, 0);
isa = xtensa_default_isa;
- gdb_assert (BSZ >= xtensa_isa_maxlength (isa));
+ gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
ins = xtensa_insnbuf_alloc (isa);
slot = xtensa_insnbuf_alloc (isa);
@@ -2166,7 +2165,7 @@ call0_analyze_prologue (CORE_ADDR start,
if (ia + xtensa_isa_maxlength (isa) > bt)
{
ba = ia;
- bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc;
+ bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ :
body_pc;
read_memory (ba, ibuf, bt - ba);
}
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [RFA] xtensa-tdep.c ARI fix
2009-02-13 18:00 [RFA] xtensa-tdep.c ARI fix Pierre Muller
@ 2009-02-13 18:58 ` Maxim Grigoriev
2009-02-13 22:49 ` Pierre Muller
0 siblings, 1 reply; 3+ messages in thread
From: Maxim Grigoriev @ 2009-02-13 18:58 UTC (permalink / raw)
To: Pierre Muller; +Cc: gdb-patches, maxim2405
Hello Pierre,
>> Maxim, is this OK?
Yes. Thank you very much for noticing this issue and making a clean-up.
-- Maxim
Pierre Muller wrote:
> Current ARI
> has one critical "hash" failure:
>
> hash 1 Do not use ` #...', instead use `#...'
> (some compilers only correctly parse a C preprocessor directive when `#' is
> the first character on the line)
>
> coming from xtensa-tdep.c
> It appears that the offending line is
> #define BSZ 32 /* Instruction buffer size. */
> I could have removed the starting spaces and commit the change as obvious,
> but there is already a macro defining the instruction buffer size
> at line 1050:
> #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
>
> So I propose here a patch getting rid of the BSZ macro
> and using XTENSA_ISA_BSZ in place of BSZ
> in call0_analyse_prologue function.
>
> Maxim, is this OK?
>
>
> 2009-02-13 Pierre Muller <muller@ics.u-strasbg.fr>
>
> * xtensa-tdep.c (call0_analyze_prologue): Delete BSZ macro.
> Replace BSZ macro uses by XTENSA_ISA_BSZ macro.
>
>
>
> Index: xtensa-tdep.c
> ===================================================================
> RCS file: /cvs/src/src/gdb/xtensa-tdep.c,v
> retrieving revision 1.30
> diff -u -p -r1.30 xtensa-tdep.c
> --- xtensa-tdep.c 3 Jan 2009 05:57:54 -0000 1.30
> +++ xtensa-tdep.c 13 Feb 2009 16:44:55 -0000
> @@ -2092,8 +2092,7 @@ call0_analyze_prologue (CORE_ADDR start,
> CORE_ADDR ia; /* Current insn address in prologue. */
> CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
> CORE_ADDR bt; /* Current address at top+1 of insn
> buffer.
> */
> - #define BSZ 32 /* Instruction buffer size. */
> - char ibuf[BSZ]; /* Instruction buffer for decoding prologue. */
> + char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue.
> */
> xtensa_isa isa; /* libisa ISA handle. */
> xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
> xtensa_format ifmt; /* libisa instruction format. */
> @@ -2153,7 +2152,7 @@ call0_analyze_prologue (CORE_ADDR start,
> if (!xtensa_default_isa)
> xtensa_default_isa = xtensa_isa_init (0, 0);
> isa = xtensa_default_isa;
> - gdb_assert (BSZ >= xtensa_isa_maxlength (isa));
> + gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
> ins = xtensa_insnbuf_alloc (isa);
> slot = xtensa_insnbuf_alloc (isa);
>
> @@ -2166,7 +2165,7 @@ call0_analyze_prologue (CORE_ADDR start,
> if (ia + xtensa_isa_maxlength (isa) > bt)
> {
> ba = ia;
> - bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc;
> + bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ :
> body_pc;
> read_memory (ba, ibuf, bt - ba);
> }
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* RE: [RFA] xtensa-tdep.c ARI fix
2009-02-13 18:58 ` Maxim Grigoriev
@ 2009-02-13 22:49 ` Pierre Muller
0 siblings, 0 replies; 3+ messages in thread
From: Pierre Muller @ 2009-02-13 22:49 UTC (permalink / raw)
To: 'Maxim Grigoriev'; +Cc: gdb-patches
Thanks,
I checked the patch in.
Pierre Muller
Pascal language support maintainer for GDB
> -----Message d'origine-----
> De : Maxim Grigoriev [mailto:maxim@tensilica.com]
> Envoyé : Friday, February 13, 2009 7:42 PM
> À : Pierre Muller
> Cc : gdb-patches@sourceware.org; maxim2405@gmail.com
> Objet : Re: [RFA] xtensa-tdep.c ARI fix
>
> Hello Pierre,
>
> >> Maxim, is this OK?
>
> Yes. Thank you very much for noticing this issue and making a clean-up.
>
> -- Maxim
>
>
> Pierre Muller wrote:
> > Current ARI
> > has one critical "hash" failure:
> >
> > hash 1 Do not use ` #...', instead use `#...'
> > (some compilers only correctly parse a C preprocessor directive when
> `#' is
> > the first character on the line)
> >
> > coming from xtensa-tdep.c
> > It appears that the offending line is
> > #define BSZ 32 /* Instruction buffer size. */
> > I could have removed the starting spaces and commit the change as
> obvious,
> > but there is already a macro defining the instruction buffer size
> > at line 1050:
> > #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
> >
> > So I propose here a patch getting rid of the BSZ macro
> > and using XTENSA_ISA_BSZ in place of BSZ
> > in call0_analyse_prologue function.
> >
> > Maxim, is this OK?
> >
> >
> > 2009-02-13 Pierre Muller <muller@ics.u-strasbg.fr>
> >
> > * xtensa-tdep.c (call0_analyze_prologue): Delete BSZ macro.
> > Replace BSZ macro uses by XTENSA_ISA_BSZ macro.
> >
> >
> >
> > Index: xtensa-tdep.c
> > ===================================================================
> > RCS file: /cvs/src/src/gdb/xtensa-tdep.c,v
> > retrieving revision 1.30
> > diff -u -p -r1.30 xtensa-tdep.c
> > --- xtensa-tdep.c 3 Jan 2009 05:57:54 -0000 1.30
> > +++ xtensa-tdep.c 13 Feb 2009 16:44:55 -0000
> > @@ -2092,8 +2092,7 @@ call0_analyze_prologue (CORE_ADDR start,
> > CORE_ADDR ia; /* Current insn address in
> prologue. */
> > CORE_ADDR ba = 0; /* Current address at base of insn
> buffer. */
> > CORE_ADDR bt; /* Current address at top+1 of
> insn
> > buffer.
> > */
> > - #define BSZ 32 /* Instruction buffer size. */
> > - char ibuf[BSZ]; /* Instruction buffer for decoding
> prologue. */
> > + char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding
> prologue.
> > */
> > xtensa_isa isa; /* libisa ISA handle. */
> > xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot.
> */
> > xtensa_format ifmt; /* libisa instruction format. */
> > @@ -2153,7 +2152,7 @@ call0_analyze_prologue (CORE_ADDR start,
> > if (!xtensa_default_isa)
> > xtensa_default_isa = xtensa_isa_init (0, 0);
> > isa = xtensa_default_isa;
> > - gdb_assert (BSZ >= xtensa_isa_maxlength (isa));
> > + gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
> > ins = xtensa_insnbuf_alloc (isa);
> > slot = xtensa_insnbuf_alloc (isa);
> >
> > @@ -2166,7 +2165,7 @@ call0_analyze_prologue (CORE_ADDR start,
> > if (ia + xtensa_isa_maxlength (isa) > bt)
> > {
> > ba = ia;
> > - bt = (ba + BSZ) < body_pc ? ba + BSZ : body_pc;
> > + bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ
> :
> > body_pc;
> > read_memory (ba, ibuf, bt - ba);
> > }
> >
> >
^ permalink raw reply [flat|nested] 3+ messages in thread
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2009-02-13 18:58 ` Maxim Grigoriev
2009-02-13 22:49 ` Pierre Muller
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