From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id wqJTGuSDcWZOtDwAWB0awg (envelope-from ) for ; Tue, 18 Jun 2024 08:56:04 -0400 Authentication-Results: simark.ca; dkim=pass (2048-bit key; unprotected) header.d=lists.lttng.org header.i=@lists.lttng.org header.a=rsa-sha256 header.s=default header.b=AIZA+N+A; dkim-atps=neutral Received: by simark.ca (Postfix, from userid 112) id 451671E0C1; Tue, 18 Jun 2024 08:56:04 -0400 (EDT) Received: from lists.lttng.org (lists.lttng.org [167.114.26.123]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id C10FD1E030 for ; Tue, 18 Jun 2024 08:56:01 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=lists.lttng.org; s=default; t=1718715361; bh=g2+l0ri3GHxdtZnY16Y99suQIb9uGp5vVH8TWhR6m5I=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=AIZA+N+AcnfuH7LNY80CAIvb4kW9eGti7kBAAy2NFtawRMXwzAFDG+OJI15GhLBPN xPDlXCA63dOSF+Y/9FEaMQjKcIQOvXcboKaQhpNcOSIaBAHkANQ/ZV9277NY6aKqdK rT9UdJ9JERt6Lts3kQscHEI2HdTv1DLP2wBYabRmiy6EDhvGarP18j4H82vuEiKgbc f07d8u1e8e2TrIKHuFXlEFIwct2UyFBNzLlQOdYaRBkmMmqI/g6qZz106QXXEkV6s3 fOwydwvEBit/MvBrcLaWc8K1ucMTyC+anpG6+5jNjtkRTVUk58FIyaeROEbk/0mj9d pWwp1tc+21vEA== Received: from lists-lttng01.efficios.com (localhost [IPv6:::1]) by lists.lttng.org (Postfix) with ESMTP id 4W3RZT0hJLz3pT; Tue, 18 Jun 2024 08:56:01 -0400 (EDT) Received: from mail-yw1-x112f.google.com (mail-yw1-x112f.google.com [IPv6:2607:f8b0:4864:20::112f]) by lists.lttng.org (Postfix) with ESMTPS id 4W3RZR3sYSz44t for ; Tue, 18 Jun 2024 08:55:59 -0400 (EDT) Received: by mail-yw1-x112f.google.com with SMTP id 00721157ae682-6326f1647f6so37588007b3.0 for ; Tue, 18 Jun 2024 05:55:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718715358; x=1719320158; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=z4nPsOwxKkjkoZUWmDH5IUDme0arwCaNQqvkJ5pFhRE=; b=gGpmcgBIVYYtWLocBkITobc04PS1RXNUl7ndze8Bz31u/Z9uQlFzyd7bqxtA7a0mic rUrVRIiOylyFhES+F+S6+SGCqIaIK265XOPkvgZJ9hHK4/YeExukmkNLABpKIDBVRVIK RoNYSuTX2iFIOfvrPyG/RlrlcBJAzVUsF5L5V1bNB/6D6o2Rwy7g3BbI4aI0RVABP5Sv a4eebmkH/KRLXZcn5NS678hAqO9LYNu1pqOI3QEehBJ0xrZ+t4K9uGN3vP2Qqhayau/G VxiGm/RVxDO7ZKM+gAL7r4e5O1mt+fKvewO+nZvitbL5uGRk+vDHmqYGXVZT6NsPMSYI VeLw== X-Gm-Message-State: AOJu0YxhUyD38j+k12ORISGvkfw7hDrRF5FpwAk4iusYjGk30kS0bDrY lOhrb1rfIhYshDkrA/gDQSmI8tr69A7fQlKriALK70SaR1fZomhZvUP7LEydxtxepE0Y+//pSqZ UbEGfzXIzCtoP5XWJkNilFrMeiK0K4Nlc X-Google-Smtp-Source: AGHT+IHbP8/ULhovlLAB50UlA1UOlJmyqfCHPIenKy9pIu2kkvyEPYaxVNTEPJLa7/+8Wc/Hc0iPf+zLbIZPWSXGAwI= X-Received: by 2002:a81:f101:0:b0:620:3c10:527a with SMTP id 00721157ae682-63222b53693mr118049377b3.15.1718715358327; Tue, 18 Jun 2024 05:55:58 -0700 (PDT) MIME-Version: 1.0 Date: Tue, 18 Jun 2024 18:25:50 +0530 Message-ID: To: lttng-dev@lists.lttng.org Subject: [lttng-dev] Is it possible to disable recording the CPU id for USTs? X-BeenThere: lttng-dev@lists.lttng.org X-Mailman-Version: 2.1.39 Precedence: list List-Id: LTTng development list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Aditya Kurdunkar via lttng-dev Reply-To: Aditya Kurdunkar Content-Type: multipart/mixed; boundary="===============5895462166588085941==" Errors-To: lttng-dev-bounces@lists.lttng.org Sender: "lttng-dev" --===============5895462166588085941== Content-Type: multipart/alternative; boundary="000000000000673f17061b299a2d" --000000000000673f17061b299a2d Content-Type: text/plain; charset="UTF-8" Hello, Please bear with me if this is a naive question. I am working on an embedded ARM chip (1GB ram, 2CPUs) where I want to collect trace events for a long duration of time. From the research that I have done (mostly reading papers on LTTng tracing, conference talks and documentation) I have seen it mentioned that for ARM the overhead is greater because the system call to get the CPU is quite slow. In my use case I am okay with not having this information. The current benchmarks show a 3 microsecond overhead of a single tracepoint on ARM in comparison to 150ns on a x86 machine. Hence, my question is: Is it possible to disable recording the CPU somehow? Any suggestions for decreasing the overhead other than this are welcome. Regards, Aditya --000000000000673f17061b299a2d Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hello,

Please bear with me if= this is a naive question. I am working on an embedded ARM chip (1GB ram, 2= CPUs) where I want to collect trace events for a long duration of time. Fro= m the research that I have done (mostly reading papers on LTTng tracing, c= onference talks and documentation) I have seen it mentioned that for ARM th= e overhead is greater because the system call to get the CPU is quite slow.= In my use case I am okay with not having=C2=A0 this information. The curre= nt benchmarks show a 3 microsecond overhead of a single tracepoint on ARM i= n comparison to 150ns on a x86 machine. Hence, my question is: Is it possib= le to disable recording the CPU somehow? Any suggestions for decreasing the= overhead other than this are welcome.

Regards,
Adity= a
--000000000000673f17061b299a2d-- --===============5895462166588085941== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ lttng-dev mailing list lttng-dev@lists.lttng.org https://lists.lttng.org/cgi-bin/mailman/listinfo/lttng-dev --===============5895462166588085941==--