From mboxrd@z Thu Jan  1 00:00:00 1970
From: pbonzini@redhat.com (Paolo Bonzini)
Date: Fri, 12 Nov 2010 15:39:21 +0100
Subject: [ltt-dev] [PATCH 2/2] introduce uatomic_and and uatomic_or
In-Reply-To: <20101112123856.GA31489@Krystal>
References: <1289552247-18130-1-git-send-email-pbonzini@redhat.com>
	<1289552247-18130-3-git-send-email-pbonzini@redhat.com>
	<20101112120846.GB27929@Krystal> <4CDD2F69.7020407@redhat.com>
	<20101112121900.GA29642@Krystal> <4CDD31E7.1050500@redhat.com>
	<4CDD32AC.2050308@redhat.com> <20101112123018.GB30826@Krystal>
	<20101112123856.GA31489@Krystal>
Message-ID: <4CDD5199.2010003@redhat.com>

On 11/12/2010 01:38 PM, Mathieu Desnoyers wrote:
> But I wonder if, on any architecture, there is a significantly better
> way to implement:
>
> uatomic_xchg_add/uatomic_xchg_or (returning the old value)
                ^^^

Assuming you mean "and" (for "add" there is an obvious benefit on x86 
which has XADD), there is some benefit on LL/SC architectures, where you 
can do

	ll  reg, mem
	and temp, reg, val
	sc  mem, temp
	<redo upon lost reservation>
	isync

instead of this more complicated code using cmpxchg:

   1:
	ld  temp1, mem		; normal load of old value
	and temp2, temp1, val	; compute new one
   2:
	ll  reg, mem		; reg = cmpxchg(&x, temp1, temp2)
	cmp reg, temp1
	bne 1b
	sc  mem, temp2
	<redo from 2 upon lost reservation>
	isync

Actually, what you get from uatomic_ppc.h is even a bit worse:

   1:
	ld  temp1, mem		; normal load of old value
	and temp2, temp1, val	; compute new one
   2:
	ll  reg, mem		; reg = cmpxchg(&x, temp1, temp2)
	cmp reg, temp1
	bne 3f
	sc  mem, temp2
	<redo from 2 upon lost reservation>
	isync
   3:
	cmp reg, temp1   	; compiler cannot optimize jump-to-jump
	bne 1b		 	; because "bne 3f" is inside an asm

Paolo