From mboxrd@z Thu Jan 1 00:00:00 1970 From: pbonzini@redhat.com (Paolo Bonzini) Date: Fri, 19 Feb 2010 20:22:46 +0100 Subject: [ltt-dev] [PATCH 04/12] define sync_core for x86 PIC In-Reply-To: <1266607374-1107-1-git-send-email-pbonzini@redhat.com> References: <1266607374-1107-1-git-send-email-pbonzini@redhat.com> Message-ID: <1266607374-1107-5-git-send-email-pbonzini@redhat.com> Pushing/popping the reserved ebx register is surely less expensive than a memory barrier. Note that since ebx is a callee-save register, this is even safe for signals (i.e. it would be safe even if we needed the value that cpuid puts in %%ebx). Signed-off-by: Paolo Bonzini Acked-by: Mathieu Desnoyers --- urcu/arch_x86.h | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/urcu/arch_x86.h b/urcu/arch_x86.h index c4674de..64cc026 100644 --- a/urcu/arch_x86.h +++ b/urcu/arch_x86.h @@ -49,9 +49,13 @@ extern "C" { /* * Serialize core instruction execution. Also acts as a compiler barrier. - * Cannot use cpuid on PIC because it clobbers the ebx register; - * error: PIC register 'ebx' clobbered in 'asm' + * On PIC ebx cannot be clobbered */ +#ifdef __PIC__ +#define sync_core() \ + asm volatile("push %%ebx; cpuid; pop %%ebx" \ + : : : "memory", "eax", "ecx", "edx"); +#endif #ifndef __PIC__ #define sync_core() \ asm volatile("cpuid" : : : "memory", "eax", "ebx", "ecx", "edx"); -- 1.6.6