From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19386 invoked by alias); 17 Jun 2003 05:34:57 -0000 Mailing-List: contact gdb-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sources.redhat.com Received: (qmail 19310 invoked from network); 17 Jun 2003 05:34:52 -0000 Received: from unknown (HELO mms2.broadcom.com) (63.70.210.59) by sources.redhat.com with SMTP; 17 Jun 2003 05:34:52 -0000 Received: from 63.70.210.1 by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (MMS v5.5.2)); Mon, 16 Jun 2003 22:31:22 -0700 Received: from mail-sj1-5.sj.broadcom.com (mail-sj1-5.sj.broadcom.com [10.16.128.236]) by mon-irva-11.broadcom.com (8.9.1/8.9.1) with ESMTP id WAA00121; Mon, 16 Jun 2003 22:34:18 -0700 (PDT) Received: from ldt-sj3-010.sj.broadcom.com (ldt-sj3-010 [10.21.64.10]) by mail-sj1-5.sj.broadcom.com (8.12.9/8.12.9/SSF) with ESMTP id h5H5Ydov026632; Mon, 16 Jun 2003 22:34:39 -0700 (PDT) Received: (from cgd@localhost) by ldt-sj3-010.sj.broadcom.com ( 8.11.6/8.9.3) id h5H5Yda07052; Mon, 16 Jun 2003 22:34:39 -0700 X-Authentication-Warning: ldt-sj3-010.sj.broadcom.com: cgd set sender to cgd@broadcom.com using -f To: drow@mvista.com cc: "Andrew Cagney" , gdb@sources.redhat.com Subject: Re: MIPS o32 ABI spec, $fp1 valid? References: <3EEE0E2D.8050805@redhat.com> <20030616185054.GA30776@nevyn.them.org> From: cgd@broadcom.com Date: Tue, 17 Jun 2003 05:34:00 -0000 In-Reply-To: Message-ID: User-Agent: Gnus/5.09 (Gnus v5.9.0) Emacs/21.2 MIME-Version: 1.0 X-WSS-ID: 12F078201101866-01-01 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-SW-Source: 2003-06/txt/msg00332.txt.bz2 At Mon, 16 Jun 2003 18:52:04 +0000 (UTC), "Daniel Jacobowitz" wrote: > Co-processor 1 adds 32 32-bit floating-point general registers and a > 32-bit control/status register. Each even/odd pair of the 32 > floating-point general registers can be used as either a 32-bit > single-precision floating-point register or as a 64-bit > double-precision floating-point register. For single-precision values, > the even-numbered floating-point register holds the value. For > double-precision values, the even-numbered floating-point register > holds the least significant 32 bits of the value and the odd-numbered > floating-point register holds the most significant 32 bits of the > value. This is always true, regardless of the byte ordering conventions > in use ( big endian or little endian). FYI, the above agrees with my reading of Kane (see http://sources.redhat.com/ml/gdb-patches/2003-06/msg00555.html ). The ISBN is 0135847494. it can be found used in lots of places for approx $10. I paid more for mine 10+ years ago. 8-) > Which is actually pretty ambiguous, not really at all: "Each even/odd pair... as either _a_ 32-bit ..." etc. Kane makes clear: In the following pages, the notation FGR refers to the FPA's general register 0 through 31, and FPR refers ot the FPA's floating-point registers (FPR 0 through 30) which are formed by concatenation of FGR's[sic] (as described in Chapter 6). Chapter 6 really makes quite clear that there are 16 FGRs. cgd