From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19773 invoked by alias); 20 Oct 2006 21:18:09 -0000 Received: (qmail 19762 invoked by uid 22791); 20 Oct 2006 21:18:06 -0000 X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (65.74.133.4) by sourceware.org (qpsmtpd/0.31) with ESMTP; Fri, 20 Oct 2006 21:18:04 +0000 Received: (qmail 26894 invoked from network); 20 Oct 2006 21:18:01 -0000 Received: from unknown (HELO localhost) (jimb@127.0.0.2) by mail.codesourcery.com with ESMTPA; 20 Oct 2006 21:18:01 -0000 To: Andrew STUBBS Cc: GDB List Subject: Re: Breakpoints in delay slots References: <453608FC.2040201@st.com> From: Jim Blandy Date: Fri, 20 Oct 2006 21:18:00 -0000 In-Reply-To: <453608FC.2040201@st.com> (Andrew STUBBS's message of "Wed, 18 Oct 2006 11:59:08 +0100") Message-ID: User-Agent: Gnus/5.11 (Gnus v5.11) Emacs/22.0.50 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-IsSubscribed: yes Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org X-SW-Source: 2006-10/txt/msg00163.txt.bz2 Andrew STUBBS writes: > The problem occurs when a breakpoint is placed on the delay slot > instruction. This can happen when this instruction happens to be the > first instruction of a source line, or when the user sets the > breakpoint on a specific address. Yeah. As others have said, this is a pain. The important thing to note here is that there's a bit of processor state that I gather you don't have access to on the SH4 --- the 'next PC', to which control will go after the current instruction. If the SH4 doesn't provide GDB enough information to predict where non-exceptional flow should go on resumption, or if it exists but the kernel doesn't make it available to GDB, then that's the fundamental bug. The SPARC (or am I thinking of the HPPA?) actually makes this explicit, with an NPC ("next pc") register. In a delay slot, PC will point at the instruction in the delay slot, and NPC points to the target of the branch. MIPS effectively provides the same information with the bit in the cause register.