From: Samuel Bronson <naesten@gmail.com>
To: gdb@sources.redhat.com
Subject: Re: Towards better x86 system debugging support
Date: Fri, 29 May 2009 19:20:00 -0000 [thread overview]
Message-ID: <loom.20090529T190319-951@post.gmane.org> (raw)
In-Reply-To: <49634AE3.4020400@web.de>
Jan Kiszka <jan.kiszka <at> web.de> writes:
> Mark Kettenis wrote:
> >> From: Jan Kiszka <jan.kiszka <at> web.de>
> >> Unfortunately, the x86 support is incomplete in so far that neither the
> >> gdb remote protocol nor the gdb backend are aware of most special
> >> registers x86 system-level software uses. This comes with several drawbacks:
> >> o Current code bit width (16, 32 or 64) is unknown to the debugger,
> >> so correct disassembling is not automatically possible
> >> o Real mode cannot be detected, which would include setting 16 bit
> >> disassembly mode and calculating segment bases appropriately
> >> o Only flat memory models are supported and debugging becomes very
> >> hairy when some segment uses a non-zero base address - note that this
> >> also prevents support for TLS variable lookup (which is GS or
> >> FS-based)
> >> As a first step toward enhanced x86 support, I think there is a need for
> >> an extended register set in the remote protocol. The following registers
> >> should be added:
> >> o GDTR, LDTR, IDTR, TR (visible part, ie. selector value)
> >> o CR0..4
> >> o DR0..7
> >> o selected MSRs, at least
> >> - IA32_EFER (64-bit mode detection)
> >> - IA32_FS_Base (TLS)
> >> - IA32_GS_Base (TLS)
> >> - IA32_KernelGSbase (TLS)
> >> o Shadow states of segment registers, GDTR, LDTR, IDTR and TR
> >> (relevant for virtual targets where the VM often has access to these
> >> hidden states, helpful when debugging targets that modify in-use
> >> descriptor table entries)
These things have also been bothering me lately, along with GDB's poor handling
of interrupt handlers, namely:
o the "finish" command doesn't work in an interrupt-handler frame
o GDB (presumably) does not notice when a frame's (interrupt) return CS:EIP
is at a different privilege level from that frame's own CS:EIP, which it
would need to do in order to correctly unwind the calling frame's SS:ESP,
which are stored on the stack in this situation rather than inferred
based on the present frame
Have you made any progress on any of this, Jan?
next prev parent reply other threads:[~2009-05-29 19:20 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-01-04 13:34 Jan Kiszka
2009-01-05 3:44 ` Daniel Jacobowitz
2009-01-05 8:52 ` GDB MI and actual type of a pointer or reference Elmenthaler, Jens
2009-01-05 9:36 ` Towards better x86 system debugging support Jan Kiszka
2009-01-06 15:14 ` Daniel Jacobowitz
2009-01-05 20:20 ` Mark Kettenis
2009-01-06 12:13 ` Jan Kiszka
2009-05-29 19:20 ` Samuel Bronson [this message]
2009-05-31 9:36 ` Jan Kiszka
2009-01-06 23:59 ` Doug Evans
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