From: Paul Walmsley via Gdb <gdb@sourceware.org>
To: Andy Chiu <tchiu@tenstorrent.com>
Cc: Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Oleg Nesterov <oleg@redhat.com>,
linux-riscv@lists.infradead.org, andybnac@gmail.com,
Sergey Matyukevich <geomatsi@gmail.com>,
gdb@sourceware.org, dfustini@oss.tenstorrent.com,
greentime.hu@sifive.com,
Yong-Xuan Wang <yongxuan.wang@sifive.com>,
daichengrong <daichengrong@iscas.ac.cn>,
Deepak Gupta <debug@rivosinc.com>
Subject: Re: [PATCH v6 6/8] riscv: vector: adjust ptrace and signal behavior for INITIAL state
Date: Tue, 3 Nov 2026 20:46:49 -0700 (MST) [thread overview]
Message-ID: <d459a3ff-7834-7a8d-92d3-339572ee4012@kernel.org> (raw)
In-Reply-To: <20260918215154.2481482-7-tchiu@tenstorrent.com>
Hi Andy,
On Fri, 18 Sep 2026, Andy Chiu wrote:
> The last patch introduced the INITIAL vector state to avoid saving and
> restoring vector registers across syscall boundaries. However, this
> optimization did not fully account for the ptrace and signal handling
> interfaces.
>
> As a result, two issues emerged:
> 1. Ptrace reads at syscall stop could observe stale, non-nulled
> registers.
> 2. Modifications to the ucontext through signal interface during a
> syscall stop would be overwritten by the vector discaring macro.
If patch 5 introduces bugs that then need to be fixed by this patch 6,
then either the two patches should be combined, or patch 5 needs to be
rewritten so that it doesn't introduce bugs. That way, bisectability is
preserved without introducing unexpected regressions. Care to take a look
and figure out what the best approach is in this case?
thanks,
- Paul
prev parent reply other threads:[~2026-11-04 3:47 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260918215154.2481482-1-tchiu@tenstorrent.com>
2026-09-18 21:51 ` Andy Chiu via Gdb
2026-11-04 3:46 ` Paul Walmsley via Gdb [this message]
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