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charset="us-ascii" MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN7PR11MB7638.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7cba9d95-94ba-4bbb-b468-08dca0d458c5 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Jul 2024 11:35:06.2535 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 4UTOtYVOeZ6ehDQfJRQA1AlTuqJbZfqn0OoUunfPvIW62pfT3QcjxI1n1dyJpQ5zhQ1c/SUtmahB12R0QKqQIPJZpeva5enzJYOeFkC9CwA= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR11MB7531 X-OriginatorOrg: intel.com Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gdb@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: "Schimpe, Christina via Gdb" Reply-To: "Schimpe, Christina" Errors-To: gdb-bounces~public-inbox=simark.ca@sourceware.org Sender: "Gdb" > * Christina Schimpe: > = > > We are currently working on the implementation of the shadow stack > backtrace. > > This is how we would print a shadow stack backtrace for signals: > > > > ~~~ > > (gdb) bt shadow > > #0 0x00007ffff7c54d90 in __restore_rt from /lib64/libc.so.6 > > #1 0x80007ffff79fffd8 > > #2 0x00007ffff7c54ce6 in __GI_raise at ../sysdeps/posix/raise.c:27 > > #3 0x000000000040115d in main at /tmp/amd64-shadow-stack-signal.c:32 > > [...] > > ~~~ > = > > This would be the corresponding ordinary stack: > > ~~~ > > (gdb) bt > > #0 handler (signo=3D10) at /tmp/amd64-shadow-stack-signal.c:25 > > #1 > > #2 __pthread_kill_implementation ([...]) at pthread_kill.c:44 > > #3 0x00007ffff7ca15f3 in __pthread_kill_internal (signo=3D10, > > threadid=3D) at pthread_kill.c:78 > > #4 0x00007ffff7c54ce6 in __GI_raise (sig=3D10) at > > ../sysdeps/posix/raise.c:26 > > #5 0x000000000040115d in main () at > > /tmp/amd64-shadow-stack-signal.c:31 > > ~~~ > > Do you see much value in combining the outputs? > = > The difference is that the shadow stack backtrace does not contain the > interrupted instruction, so frame #2 in the traditional backtrace. This = is more > important for CPU-generated signals such as division by zero or invalid > memory access, where you really want to see the fault address in the > backtrace. > = > > The elements on the shadow stack are following the description of the > > linux kernel for signals: > > "When a signal happens, the old pre-signal state is pushed on the stack. > > When shadow stack is enabled, the shadow stack specific state is > > pushed onto the shadow stack. Today this is only the old SSP (shadow > > stack pointer), pushed in a special format with bit 63 set." > > (https://docs.kernel.org/arch/x86/shstk.html) > > > > Frame 1 contains the old SSP with bit 63 set. > = > I would like the kernel to push the address of the interrupted instructio= n as > well, potentially with additional flag markup. Or maybe it's so early th= at we > don't need it. The signal return path would have pop it off the stack an= d not > validate it because I think it's an expected use case to redirect executi= on from > a signal handler by patching the signal context. Alternatively, the kern= el > could push the address of the signal context, which might be even more > useful. I think it would be useful if the shadow stack contained all the= data > needed to implement the glibc backtrace function, not because glibc is > important, but because it seems to be a good indicator what programmers > expect from a backtrace. > = > We also need to figure out how this interacts with LAM. Does the CPU push > tagged addresses onto the shadow stack? = No, I don't think so. For LAM only tagged data pointers are supported. = Christina Intel Deutschland GmbH Registered Address: Am Campeon 10, 85579 Neubiberg, Germany Tel: +49 89 99 8853-0, www.intel.de Managing Directors: Sean Fennelly, Jeffrey Schneiderman, Tiffany Doon Silva Chairperson of the Supervisory Board: Nicole Lau Registered Office: Munich Commercial Register: Amtsgericht Muenchen HRB 186928