From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 7216 invoked by alias); 17 Feb 2004 04:49:01 -0000 Mailing-List: contact gdb-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sources.redhat.com Received: (qmail 7204 invoked from network); 17 Feb 2004 04:49:00 -0000 Received: from unknown (HELO hotmail.com) (64.4.16.120) by sources.redhat.com with SMTP; 17 Feb 2004 04:49:00 -0000 Received: from mail pickup service by hotmail.com with Microsoft SMTPSVC; Mon, 16 Feb 2004 20:48:59 -0800 Received: from 203.200.20.226 by law11-oe16.law11.hotmail.com with DAV; Tue, 17 Feb 2004 04:48:59 +0000 X-Originating-IP: [203.200.20.226] X-Originating-Email: [mohanlaljangir@hotmail.com] X-Sender: mohanlaljangir@hotmail.com Reply-To: "mohanlal jangir" From: "mohanlal jangir" To: "Andrew Cagney" Cc: References: <402CE55C.6070605@gnu.org> <4031535A.7080500@gnu.org> Subject: Re: hardware support for gdb? Date: Tue, 17 Feb 2004 04:49:00 -0000 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-ID: X-OriginalArrivalTime: 17 Feb 2004 04:48:59.0948 (UTC) FILETIME=[5BC656C0:01C3F511] X-SW-Source: 2004-02/txt/msg00186.txt.bz2 > > > > Really!! Does even single stepping also not require any hardware support? > > I'm not sure what you mean by hardware support. The instruction set > architecture needs to provide a breakpoint instruction. A single-step > mechanism is useful but not an absolute requirement - GDB can use > software singlestep (although I suspect that code has bitrotten). > > Andrew > Thanks Andrew for your prompt replies. I was reading an article on "how gdb works". This is a paragraph from that: The Remote Serial Protocol's step command is a bit more challenging, especially when the target processor doesn't provide a "trace bit" or similar functionality (For example, Motorola 683xx processors contain the ability to trap on instruction execution and/or changes in program flow; this feature is controlled by the "trace enable" bits, T1 and T0, in the processor's status register). In these cases, the only alternative is for the stub to disassemble the instruction about to be executed so that it can determine where the program is going to go next. What I understood from this paragraph is that, if a target processor provide "trace bit" kind of functionality, gdb developer's life is easier otherwise he has to do some more work(disassembling of instruction). Am I right? Could you please explain a little about "trace bit" or similar functionality? Is it the breakpoint instruction, you mentioned about? Regards Mohanlal