From: Xiaozhu Meng <mxz297@gmail.com>
To: gdb@sourceware.org
Subject: icache-dcache coherence on ARM
Date: Mon, 06 May 2019 19:30:00 -0000 [thread overview]
Message-ID: <CALjUE3-2G9qiL+Ntp2QeCuY5aaiZQbo0YRAmo16ziFFN40KRwA@mail.gmail.com> (raw)
Hi,
I am reading gdb's source code to hopefully get answers for a question that
I have in my other project.
On ARM, the architecture does not guarantee that icache and dcache are
coherent. When GDB writes a software breakpoint into the inferior's address
space, is it possible that the inferior executes outdated code in icache
and thus miss the software breakpoint?
I try to search around the gdb code base to understand whether GDB flushes
icache or not, but could not find answers.
I appreciate any feedback!
Thanks,
--Xiaozhu
next reply other threads:[~2019-05-06 19:30 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-06 19:30 Xiaozhu Meng [this message]
2019-05-06 20:52 ` John Baldwin
2019-05-06 21:17 ` Xiaozhu Meng
2019-05-06 21:37 ` John Baldwin
2019-05-07 2:52 ` Xiaozhu Meng
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