From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 87354 invoked by alias); 16 Jun 2015 05:22:02 -0000 Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org Received: (qmail 87335 invoked by uid 89); 16 Jun 2015 05:22:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-oi0-f49.google.com Received: from mail-oi0-f49.google.com (HELO mail-oi0-f49.google.com) (209.85.218.49) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Tue, 16 Jun 2015 05:22:00 +0000 Received: by oiax193 with SMTP id x193so4257320oia.2 for ; Mon, 15 Jun 2015 22:21:58 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.60.131.147 with SMTP id om19mr26939270oeb.78.1434432118554; Mon, 15 Jun 2015 22:21:58 -0700 (PDT) Received: by 10.202.184.213 with HTTP; Mon, 15 Jun 2015 22:21:58 -0700 (PDT) In-Reply-To: References: <86si9trv7l.fsf@gmail.com> Date: Tue, 16 Jun 2015 05:22:00 -0000 Message-ID: Subject: Re: Is there single step debugging support being added to aarch64-linux? From: Prafull Suryawanshi To: Yao Qi Cc: Andrew Pinski , Andreas Schwab , "gdb@sourceware.org" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-06/txt/msg00036.txt.bz2 (sent too early, putting complete reply) I debugged this one and found that when compared to gdb-arm, gdb-aarch64 behaves little different. Before even invoking software-single-step operations, gdb-arm invokes Z0 packet before getting registers. But gdb-aarch64 does not do it. It sets the Z0 after reading registers. So in case gdb-arm, the Z0 is set to next pc value. But for gdb-aarch64 it sets the Z0 at current pc only. Below is logs when enabled remote_debug option. for gdb-arm infrun: resume (step=3D1, signal=3DGDB_SIGNAL_0), trap_expected=3D1, current thread [Thread 2229] at 0xc01b2ddc Sending packet: $Z0,c01b2de0,4#67...Ack For gdb-aarch64, infrun: resume (step=3D1, signal=3DGDB_SIGNAL_0), trap_expected=3D1, current thread [Thread 3462] at 0xffffffc00021014c Sending packet: $Z0,ffffffc00021014c,4#c8...Ack As we can see, gdb-aarch64 puts Z0 (breakpoint) at same place where current pc is. But gdb-arm puts breakpoint at just next pc. Then I found that gdb-arm has below output infrun: software single step trap for Thread 2229 So I implemented same for gdb-aarch64. As for KGDB code for aarch64 do not have hardware breakpoint support. (usermode does have) Not sure if that could be issue. Thanks, Prafull On Tue, Jun 16, 2015 at 10:47 AM, Prafull Suryawanshi wrote: > I debugged this one and found that when compared to gdb-arm, > gdb-aarch64 behaves little different. > Before even invoking software-single-step operations, gdb-arm invokes > Z0 packet before getting registers. > But gdb-aarch64 does not do it. It sets the Z0 after reading registers. > So in case gdb-arm, the Z0 is set to next pc value. > But for gdb-aarch64 it sets the Z0 at current pc only. > > Below is logs when enabled remote_debug option. > for gdb-arm > infrun: resume (step=3D1, signal=3DGDB_SIGNAL_0), trap_expected=3D1, curr= ent > thread [Thread 2229] at 0xc01b2ddc > Sending packet: $Z0,c01b2de0,4#67...Ack > > > For gdb-aarch64, > infrun: resume (step=3D1, signal=3DGDB_SIGNAL_0), trap_expected=3D1, curr= ent > thread [Thread 3462] at 0xffffffc00021014c > > On Mon, Jun 15, 2015 at 6:21 PM, Yao Qi wrote: >> Prafull Suryawanshi writes: >> >>> I am not sure why hw stepper not works here (might be limitation of hw >>> I am using). >> >> You'd better to check whether hw single step doesn't work in your case. >> >>> That is may be the infrun loops as it never gets stop signal. (the >>> output I earlier pasted). >>> Is it ok to provide patch for software single step like arm here? >> >> We only implement software single step on the targets don't have >> hardware single step capability, like arm. >> >>> (I am preparing one. It will have simulate aarch64 instruction set and >>> implement aarch64 version of functions of >>> arm_linux_software_single_step, arm_insert_single_step_breakpoint and >>> arm_get_next_pc.) >> >> Before you start it, better to get the reason why hw single step doesn't >> work on aarch64. >> >> -- >> Yao (=E9=BD=90=E5=B0=A7)