From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 64808 invoked by alias); 18 Nov 2016 23:44:59 -0000 Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org Received: (qmail 64794 invoked by uid 89); 18 Nov 2016 23:44:58 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.6 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.2 spammy= X-HELO: mail-it0-f50.google.com Received: from mail-it0-f50.google.com (HELO mail-it0-f50.google.com) (209.85.214.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 18 Nov 2016 23:44:47 +0000 Received: by mail-it0-f50.google.com with SMTP id c20so49271245itb.0 for ; Fri, 18 Nov 2016 15:44:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=nqHEOgGNXVaQU1pG6OHE7HWjzjbcABtqfB37GhVWPTk=; b=GnC4Zoxd99bq+1K40c74gSy8uZsYX/pQfyDvV1O8MYYP1Ej7xqEysqidWcpcyvjCMd hOodXTMeOvuOQ/kS7B8blb16t3SUR1oClQoomV2cp2+wLNaJVZZ3rUeg0vxyiKFCCPQ8 cR6aBoJn/PPf4xp4PMVvnVjPz1CEMOHnrRG2hB+cBKD+xx4arDcJpFOQq4NMHlNesIg5 IiLMohMBCa43eFgeBfpNlUuEjz0Q0LpkZ56X3otKImcGlxQUbImgtcWiwOAaACV7jWln k/G1HDGGwPUqi9i8/oCjFReF/ZIRDyzmlEcarnW1d5vZhEcj0SB+w2+oKghFrRH6mbSk nsFg== X-Gm-Message-State: AKaTC00ua2LpT7h14iZJ8PVsblTAjV6gPUCu5DlE2vjqfcG7tsx0xTeQ/Hsu+yoqBeU86qVnfPPbWyLvDHeZOw== X-Received: by 10.36.73.195 with SMTP id e64mr996959itd.52.1479512686185; Fri, 18 Nov 2016 15:44:46 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.31.9 with HTTP; Fri, 18 Nov 2016 15:44:45 -0800 (PST) From: Tim Newsome Date: Fri, 18 Nov 2016 23:44:00 -0000 Message-ID: Subject: read target register to decide breakpoint size To: gdb Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2016-11/txt/msg00030.txt.bz2 I'm still working on RISC-V support for gdb. Any given RISC-V core may support a compressed instruction set (2 bytes per instruction as opposed to 4). There are corresponding 2-byte and 4-byte breakpoint instructions. On cores that support the compressed instruction set it is safe to just always use the 2-byte version, and there is a register I can read to tell me whether the compressed instruction set is supported. What I would like to do is read (and cache) that register when breakpoint size is determined. That seems more robust than making a decision based on ELF info, which may not reflect what is actually being executed. Is that a good idea? Are there examples of operations that read target registers to complete? Thank you, Tim