From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 91364 invoked by alias); 21 Nov 2016 18:00:42 -0000 Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org Received: (qmail 91301 invoked by uid 89); 21 Nov 2016 18:00:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.2 spammy=D*ericsson.com X-HELO: mail-it0-f46.google.com Received: from mail-it0-f46.google.com (HELO mail-it0-f46.google.com) (209.85.214.46) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 21 Nov 2016 18:00:31 +0000 Received: by mail-it0-f46.google.com with SMTP id c20so17499696itb.0 for ; Mon, 21 Nov 2016 10:00:30 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=LY2PSirSQhxfO2T/KwHLs1I+TGfGYLRGfthA89R/QQ0=; b=EjColanhgcwqZ4AlpQMhC0BauFAtaHDZqcJmypq7gzK7bRn+gZVgpJrNL5hoeYg162 r00wk+JSf2rNepEsHB5ULwg+W08kWbj1n0+40Y/KRUjDFXcaacNDqN++UJSpYBb+dDgD BiLg9MIzLyC/D32vXAfP6cOZHn0PISlHrFMNwp6IA3LmPBzFbwldc9MYkopK5uWYMH8q bD6b2faxWZqLUGNT8jmQUtHUdcbTUZ3MJdUT3uh+SQbS8lXt22Z+traBLuLT9Q0DYHxt xY1gYiZyDPioQ2Q81sJ8hcqD2ewxea4DRDWU6KDpE0a+ZCdQlXm6tKWxT9EZ8TVuPVKa sU5Q== X-Gm-Message-State: AKaTC00B7N1F0DC3VRY0soZ7H+yc1UXwrAzxDMaIsrqEOQAaa2VC3GlnKO7KnzIfl8cbGqRZG7I1L0hisUnVtw== X-Received: by 10.36.98.206 with SMTP id d197mr4040409itc.52.1479751229142; Mon, 21 Nov 2016 10:00:29 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.31.9 with HTTP; Mon, 21 Nov 2016 10:00:28 -0800 (PST) In-Reply-To: References: From: Tim Newsome Date: Mon, 21 Nov 2016 18:00:00 -0000 Message-ID: Subject: Re: read target register to decide breakpoint size To: Antoine Tremblay Cc: gdb Content-Type: text/plain; charset=UTF-8 X-IsSubscribed: yes X-SW-Source: 2016-11/txt/msg00036.txt.bz2 Thanks, Antoine! That's exactly what I was looking for. Tim On Mon, Nov 21, 2016 at 8:36 AM, Antoine Tremblay wrote: > > > Tim Newsome writes: > > > I'm still working on RISC-V support for gdb. Any given RISC-V core may > > support a compressed instruction set (2 bytes per instruction as > > opposed to 4). There are corresponding 2-byte and 4-byte breakpoint > > instructions. On cores that support the compressed instruction set it > > is safe to just always use the 2-byte version, and there is a register > > I can read to tell me whether the compressed instruction set is > > supported. What I would like to do is read (and cache) that register > > when breakpoint size is determined. That seems more robust than making > > a decision based on ELF info, which may not reflect what is actually > > being executed. > > > > Is that a good idea? Are there examples of operations that read target > > registers to complete? > > Yes actually you can check how ARM does it, it has the same kind of > problem with 3 breakpoints you can set for thumb, thumb2 and arm > instruction sets. > > See arm-tdep.c:arm_sw_breakpoint_from_kind and > arm_breakpoint_kind_from_current_state > > This is called in breakpoint.c:breakpoint_kind and it can use a register > to make the decision from the current state of that register. > > So possibly just implementing the sw_breakpoint_from_kind and > breakpoint_kind_from_current state would be ok your you. > > Regards, > Antoine Tremblay