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Tue, 27 Jan 2026 20:24:02 -0800 (PST) Received: from localhost ([2804:14d:7e39:8083:f04c:42e3:5943:38f6]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-124a9d6b906sm1070250c88.4.2026.01.27.20.24.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Jan 2026 20:24:02 -0800 (PST) To: Luis Cc: Peter Maydell , gdb@sourceware.org, Manos Pitsidianakis Subject: Re: gdb support for SME-without-SVE ? In-Reply-To: (Luis's message of "Wed, 28 Jan 2026 01:07:43 +0000") References: User-Agent: mu4e 1.12.15; emacs 30.2 Date: Wed, 28 Jan 2026 04:23:59 +0000 Message-ID: <87ldhigyao.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: gdb@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Thiago Jung Bauermann via Gdb Reply-To: Thiago Jung Bauermann Errors-To: gdb-bounces~public-inbox=simark.ca@sourceware.org Sender: "Gdb" Hello, I'm currently implementing SME-only (i.e. without SVE) support in GDB for Linux userspace debugging. It's mostly done, I just need to test a few things, polish the code and prepare the patches. I'm hoping to send the patches next week. Due to the limitations in the remote protocol that Luis mentioned below, I can't run the tests against a remote target so I'm only focusing on local debugging, unfortunately. Luis writes: > On Tue, Jan 27, 2026, 21:24 Peter Maydell wrote: > > > (2) If the CPU has SME and not SVE, presumably we should still > > expose org.gnu.gdb.aarch64.sve, as it's where the z registers are. > > What should we report "vl" as here? How about when the CPU is not > > in streaming mode and the z regs aren't accessible? > > Are there still Z registers without SVE? Yes, but they are only accessible while in streaming mode. For simplicity, if the inferior isn't in streaming mode I'm making the SVE registers available in non-streaming mode (i.e., behave as if SVE is supported) with vg = 2 as Peter mentions below. In this case, the Z registers are equivalent to the regular vector registers. > I don't think this is properly supported in any case. On top of that > SVE and SME are not properly supported via the remote protocol. In > theory it works if you don't change vg/svg mid-execution. So no SSVE > enabling etc. But in practice it does not work well. When the vg/svg > size changes you end up with overruns or garbage. > > The initial implementation of SVE assumed remote debugging wasn't > important. We're stuck with that until remote protocol enhancements > are contributed. > > Those enhancements have been proposed multiple times but there were > always downsides and it tends to die and fall into limbo. It mostly > only affects SVE and SME. Maybe AMX. I'm planning to resume this work again in the next few months. Christina and Klaus from Intel came up with a nice proposal. -- Thiago