From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 32447 invoked by alias); 22 Jul 2002 21:39:08 -0000 Mailing-List: contact gdb-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sources.redhat.com Received: (qmail 32430 invoked from network); 22 Jul 2002 21:39:06 -0000 Received: from unknown (HELO walton.kettenis.dyndns.org) (213.93.114.42) by sources.redhat.com with SMTP; 22 Jul 2002 21:39:06 -0000 Received: from elgar.kettenis.dyndns.org (elgar.kettenis.dyndns.org [192.168.0.2]) by walton.kettenis.dyndns.org (8.12.5/8.12.5) with ESMTP id g6MLcnGA050923; Mon, 22 Jul 2002 23:38:50 +0200 (CEST) (envelope-from kettenis@elgar.kettenis.dyndns.org) Received: from elgar.kettenis.dyndns.org (localhost [127.0.0.1]) by elgar.kettenis.dyndns.org (8.12.5/8.12.5) with ESMTP id g6MLco3t085680; Mon, 22 Jul 2002 23:38:50 +0200 (CEST) (envelope-from kettenis@elgar.kettenis.dyndns.org) Received: (from kettenis@localhost) by elgar.kettenis.dyndns.org (8.12.5/8.12.5/Submit) id g6MLcih5085677; Mon, 22 Jul 2002 23:38:44 +0200 (CEST) To: Andrew Cagney Cc: Jim Blandy , gdb@sources.redhat.com Subject: Re: WIP: Register doco References: <3D38AF69.7020902@ges.redhat.com> <3D39954D.1020306@ges.redhat.com> <3D39CAD1.3060106@ges.redhat.com> From: Mark Kettenis Date: Mon, 22 Jul 2002 14:39:00 -0000 In-Reply-To: Andrew Cagney's message of "Sat, 20 Jul 2002 16:40:49 -0400" Message-ID: <867kjnv3x7.fsf@elgar.kettenis.dyndns.org> X-SW-Source: 2002-07/txt/msg00228.txt.bz2 Andrew Cagney writes: > > The example of the IA-32's MMX and FP registers is a great example for > > this. The MMX registers, MM0--MM7, and the FP registers, > > ST(0)--ST(7), actually refer to the same set of eight eighty-bit > > registers, R0--R7. A reference to the floating-point register ST(i) > > becomes a reference to R((TOP + i) % 8), where TOP is a three-bit > > field in the FPU status register. But a reference to the MMX register > > MM(i) becomes a reference to the lower 64 bits of R(i) (which would be > > the mantissa of some ST(i)). > > (In the current code, ST(I) and not R(I) is stored, so we end up with > MM(I) == regcache(FP0 + (TOP + 1) % 8) :-( I'm almost ready to dust > off the patch that does this.) Oh dear, another confusing discussion about the IA-32's FP registers. While the Intel manuals talk about the registers R0--R7, the ISA doesn't really expose these. Both the old fsave and the new fxsave instructions store ST(I) and not R(I). Until the introduction of the Pentium MMX processor the R0--R7 registers really can be considered an implementation detail, and the fact that the MMX instructions set TOP to zero makes sure that as far as the MMX registers are concerned, there still is something like an identity mapping between ST(I) and R(I). In other words, I consider the fact that GDB stores ST(I) and not R(I), the right approach. Mark