From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 65794 invoked by alias); 12 Jun 2019 17:46:09 -0000 Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org Received: (qmail 65786 invoked by uid 89); 12 Jun 2019 17:46:09 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-16.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPAM_BODY1 autolearn=ham version=3.3.1 spammy=H*M:9217 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 12 Jun 2019 17:46:07 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 475F228; Wed, 12 Jun 2019 10:46:06 -0700 (PDT) Received: from [10.1.196.50] (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 247753F246; Wed, 12 Jun 2019 10:46:05 -0700 (PDT) Subject: Re: [PATCH v2 1/3] arm64/sve: Fix missing SVE/FPSIMD endianness conversions To: Dave Martin , linux-arm-kernel@lists.infradead.org Cc: gdb@sourceware.org, =?UTF-8?Q?Alex_Benn=c3=a9e?= , Will Deacon , Catalin Marinas , Peter Maydell , Zhang Lei , Alan Hayward References: <1560355234-25516-1-git-send-email-Dave.Martin@arm.com> <1560355234-25516-2-git-send-email-Dave.Martin@arm.com> From: Julien Grall Message-ID: <771b0099-9217-4e55-b73a-b03434c61655@arm.com> Date: Wed, 12 Jun 2019 17:46:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <1560355234-25516-2-git-send-email-Dave.Martin@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-SW-Source: 2019-06/txt/msg00028.txt.bz2 Hi Dave, On 12/06/2019 17:00, Dave Martin wrote: > The in-memory representation of SVE and FPSIMD registers is > different: the FPSIMD V-registers are stored as single 128-bit > host-endian values, whereas SVE registers are stored in an > endianness-invariant byte order. > > This means that the two representations differ when running on a > big-endian host. But we blindly copy data from one representation > to another when converting between the two, resulting in the > register contents being unintentionally byteswapped in certain > situations. Currently this can be triggered by the first SVE > instruction after a syscall, for example (though the potential > trigger points may vary in future). > > So, fix the conversion functions fpsimd_to_sve(), sve_to_fpsimd() > and sve_sync_from_fpsimd_zeropad() to swab where appropriate. > > There is no common swahl128() or swab128() that we could use here. > Maybe it would be worth making this generic, but for now add a > simple local hack. > > Since the byte order differences are exposed in ABI, also clarify > the docuentation. NIT: s/docuentation/documentation/ Although, it is probably too late to fix this one as Will already took the patch. [...] > diff --git a/Documentation/arm64/sve.txt b/Documentation/arm64/sve.txt > index 9940e92..6c0bed3 100644 > --- a/Documentation/arm64/sve.txt > +++ b/Documentation/arm64/sve.txt > @@ -56,6 +56,18 @@ model features for SVE is included in Appendix A. > is to connect to a target process first and then attempt a > ptrace(PTRACE_GETREGSET, pid, NT_ARM_SVE, &iov). > > +* Whenever SVE scalable register values (Zn, Pn, FFR) are exchanged in memory > + between userspace and the kernel, the register value is encoded in memory in > + an endianness-invariant layout, with bits [(8 * i + 7) : (8 * i)] encoded at > + byte offset i in from the start of the memory representation. This affects > + for example the signal frame (struct sve_context) and ptrace interface > + (struct user_sve_header) and associated data. > + > + Beware that on big-endian systems this results in a different byte order than > + for the FPSIMD V-registers, which are stored as single host-endian 128-bit > + values, with bits [(127 - 8 * i) : (120 - 8 * i)] of the register encoded at > + byte offset i. (struct fpsimd_context, struct user_fpsimd_state). > + > > 2. Vector length terminology > ----------------------------- > @@ -124,6 +136,10 @@ the SVE instruction set architecture. > size and layout. Macros SVE_SIG_* are defined [1] to facilitate access to > the members. > > +* Each scalable register (Zn, Pn, FFR) is stored in an endianness-invariant > + layout, with bits [(8 * i + 7) : (8 * i)] stored at byte offset i from the > + start of the register's representation in memory. > + > * If the SVE context is too big to fit in sigcontext.__reserved[], then extra > space is allocated on the stack, an extra_context record is written in > __reserved[] referencing this space. sve_context is then written in the > diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h > index 7b7ac0f..072ea1e 100644 > --- a/arch/arm64/include/uapi/asm/kvm.h > +++ b/arch/arm64/include/uapi/asm/kvm.h > @@ -260,6 +260,13 @@ struct kvm_vcpu_events { > KVM_REG_SIZE_U256 | \ > ((i) & (KVM_ARM64_SVE_MAX_SLICES - 1))) > > +/* > + * Register values for KVM_REG_ARM64_SVE_ZREG(), KVM_REG_ARM64_SVE_PREG() and > + * KVM_REG_ARM64_SVE_FFR() and represented in memory in an endianness- NIT: s/and represented/are represented/ I think. > + * invariant layout which differs from the layout used for the FPSIMD > + * V-registers on big-endian systems: see sigcontext.h for more explanaion. NIT: s/explanaion/explanation/ Cheers, -- Julien Grall