From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8225 invoked by alias); 3 May 2006 17:43:14 -0000 Received: (qmail 8217 invoked by uid 22791); 3 May 2006 17:43:14 -0000 X-Spam-Check-By: sourceware.org Received: from nz-out-0102.google.com (HELO nz-out-0102.google.com) (64.233.162.192) by sourceware.org (qpsmtpd/0.31) with ESMTP; Wed, 03 May 2006 17:43:11 +0000 Received: by nz-out-0102.google.com with SMTP id 8so235455nzo for ; Wed, 03 May 2006 10:43:07 -0700 (PDT) Received: by 10.65.15.19 with SMTP id s19mr1212551qbi; Wed, 03 May 2006 10:43:07 -0700 (PDT) Received: by 10.65.15.11 with HTTP; Wed, 3 May 2006 10:43:07 -0700 (PDT) Message-ID: <4d77c5f20605031043t256b1c05o3d9bb27beef8ed33@mail.gmail.com> Date: Wed, 03 May 2006 17:43:00 -0000 From: "Tzu-Chien Chiu" To: gdb@sourceware.org Subject: remote software breakpoint technical detail MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org X-SW-Source: 2006-05/txt/msg00012.txt.bz2 Hi, all. I'm new to gdb. I have a question on the remote software breakpoint implementation. Either my porting of gdb or there is a bug in our hardware implementation. We have an OpenRISC silicon (http://www.opencores.org). I'm using GDB 5.0. Suppose the instruction cache has been disabled in the very beginning. Here is what I observed: 1) the user set a breakpoint ('b') at instruction foo 2) the user continue ('c') the execution 3) gdb replaces instruction foo with a 'breakpoint instruction", which will stall the processor 4) gdb unstall the processor 5) the processor fetches the breakpoint instruction into the execution pipeline, and point pc to the next instruction 6) the breakpoint instruction is decoded, recognized, and the processor sta= lls 7) gdb restores instruction foo 8) the user issues the single instruction step ('si'), and he expects instruction foo be executed next, but... The question is: What value of pc should be expected after step 5 completes? if $pc=3D=3Dfoo+4, foo won't be executed but the following instruction, which is incorrect. if $pc=3D=3Dfoo, the breakpoint instruction _has been_ fetched into the execution pipeline at step 5, what makes the cpu to *fetch again* the instruction restored by gdb at step 7? GDB or the hardware must be designed to do so? -- Tzu-Chien Chiu - SMedia Technology Corp. URL: http://www.csie.nctu.edu.tw/~jwchiu/