Re: Question on ARM/Thumb-16 Disassembly

[Matthew Gretton-Dann <matthew.gretton-dann@arm.com>]

Jeffrey,

On 20/06/11 16:35, Jeffrey Walton wrote:
> Hi All,
>
> A couple of questions for ARM/Thumb-2. I'm working on a live iPhone,
> so I'm using Apple's GAS.

It would be useful if you could give the command line you are using - as 
I can't give precise answers without that info.  Most of the comments I 
make below are based upon the behaviour of the vanilla FSF tools, Apple 
may have changed their behaviours in ways I am unaware of.

> I've got a function generated for Thumb-16 which performs a branch
> (immediately after an ADD) based on Carry. For some reason, I'm
> getting unexpected results after the ADD - the carry flag is always
> high (ie, CY = 1 in CPSR), even when adding 0 + 0, 1 + 1, etc.
>
> Under GDB, I perform a disassembly looking for something I might have
> munged (or unexpected code generation and interactions). The first
> thing I noticed is some instructions are 4 bytes despite being in
> Thumb-16 mode (shown below). For example, the MOV at 0x00002334 is 4
> bytes.
>
> (1) Has anyone encountered a situation where a status flag gets
> pinned? The ARM Instruction Reference states the status flags are
> updated in Thumb mode (except when one or more high registers are
> specified as operands).

There are two types of assembly language syntax in GAS for ARM:

  1. 'divided' syntax - where add instruction has different semantics 
depending on whether you are in Thumb or ARM state.
  2. 'unified' syntax - where the add instruction has the same semantics 
in ARM and Thumb state.

(Look for a .syntax directive in your assembly source).

My guess is that you have written something like the following in your 
assembly code:
    add r0, r1, r2

Which would set the flags in Thumb-1 code when using divided syntax but 
does not when using unified syntax.

So the fix is to do the following instead:
    adds r0, r1, r2

[The additional 's' means set the flags].

> (2) Are 4 byte instructions expected when GCC generates Thumb-16 code?
> The ARM Instruction Reference seems to state otherwise.

GCC will generate code using all the features available in the 
instruction set for the CPU/architecture it is compiling for.  Therefore 
if you are compiling for Cortex-A8 (say) and specify -mthumb on the 
command line it will use both 16-bit and 32-bit Thumb instructions (as 
they will be available).  There is no way to tell GCC to compile for a 
CPU supporting Thumb-2 but restrict itself to just Thumb-1 instructions.

I hope this helps.

Thanks,

Matt