From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19692 invoked by alias); 11 Apr 2011 04:52:25 -0000 Received: (qmail 19679 invoked by uid 22791); 11 Apr 2011 04:52:23 -0000 X-SWARE-Spam-Status: No, hits=-0.6 required=5.0 tests=AWL,BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,RFC_ABUSE_POST,TW_EG,T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from nm26-vm1.bullet.mail.sp2.yahoo.com (HELO nm26-vm1.bullet.mail.sp2.yahoo.com) (98.139.91.231) by sourceware.org (qpsmtpd/0.43rc1) with SMTP; Mon, 11 Apr 2011 04:52:17 +0000 Received: from [98.139.91.65] by nm26.bullet.mail.sp2.yahoo.com with NNFMP; 11 Apr 2011 04:52:17 -0000 Received: from [98.139.91.9] by tm5.bullet.mail.sp2.yahoo.com with NNFMP; 11 Apr 2011 04:52:17 -0000 Received: from [127.0.0.1] by omp1009.mail.sp2.yahoo.com with NNFMP; 11 Apr 2011 04:52:16 -0000 Received: (qmail 66400 invoked by uid 60001); 11 Apr 2011 04:52:16 -0000 Message-ID: <461882.48993.qm@web112505.mail.gq1.yahoo.com> Received: from [123.238.92.157] by web112505.mail.gq1.yahoo.com via HTTP; Sun, 10 Apr 2011 21:52:16 PDT References: <341905.10459.qm@web112513.mail.gq1.yahoo.com> <208397.95006.qm@web112517.mail.gq1.yahoo.com> <4DA27006.1080607@codesourcery.com> Date: Mon, 11 Apr 2011 04:52:00 -0000 From: paawan oza Subject: Re: [PATCH] arm reversible : progress To: Yao Qi , gdb@sourceware.org In-Reply-To: <4DA27006.1080607@codesourcery.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org X-SW-Source: 2011-04/txt/msg00029.txt.bz2 Hi Yao, thanks for your comments. 1) will try to use macros for arm insns as you suggesed. 2) displaced_in_arm_mode and arm_frame_is_thumb checks T bit differenly, I = do no=20 follow frame unwind logic and checking T bit;=20 infact the arm-reference-manual which I referred; I could not find 'M' prof= ile=20 information too. hence I just checked current CSPR value. bu yes as you said; I shall change the code; 3) as of now it I have support for arm and thumb(16) only. no plan for thum= b32=20 support. 4) please also refer to FIX ME in the code, specially how o read SPSR value= ? 5) also need to know how to read coprocessor registers' value ? Regards, Oza. ----- Original Message ---- From: Yao Qi To: gdb@sourceware.org Sent: Mon, April 11, 2011 8:35:42 AM Subject: Re: [PATCH] arm reversible : progress On 04/10/2011 05:41 PM, paawan oza wrote: > Hi, >=20 > phase2 (both arm and thumb insn implemenation is complete) >=20 > Hi Tom:=20 > I have taken care of most of your comments: but could nit incorporate num= ercial=20 > > to be replaced by some meaningful symbolic names. > as I dont know what sort of symbolic names are approproate. >=20 >=20 This one looks much better than previous ones. Thanks for working on this. I am not the people to approve this patch. Some of my cents below. > + > +#define ARM_INSN_SIZE_BYTES 4=20=20=20=20 > +#define THUMB_INSN_SIZE_BYTES 2 > +#define NO_OF_TYPE_OF_ARM_INSNS 8 > +#define NO_OF_TYPE_OF_THUMB_INSNS 8 > + > +#define ARM_RECORD_ARCH_LIST_ADD_REG(regnum) \ > + record_arch_list_add_reg (arm_record.regcache, regnum) > + > +#define GET_REG_VAL(REGCACHE,NO,BUF) regcache_raw_read (REGCACHE, NO, B= UF); > + > +#define IS_IT_ARM_INSN(X) ((X & 0x00000020) >> 5) > +#define ARM_PARSE_INSN(X,BIT_POS,NO_OF_BITS) \ > + ((X >> (BIT_POS-1)) & (0xFFFFFFFF >> ((sizeof(uint32_t)*= 8) -=20 \ > + NO_OF_BITS))) There are some existing macros you can use for parsing instructions. /* Support routines for instruction parsing. */ #define submask(x) ((1L << ((x) + 1)) - 1) #define bit(obj,st) (((obj) >> (st)) & 1) #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) #define sbits(obj,st,fn) \ ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) > + > +#define INSN_S_L_BIT_NUM 21 > +#define ARM_BIT_SET(X, NUM) (((X >> (NUM-1)) & 0x00000001) =3D=3D 1)=20= =20 > +#define GET_BIT(X, NUM) (((X >> (NUM-1)) & 0x00000001)) > + GET_BIT can be replaced by `bit' I posted above. > + > +static int=20 > +handle_extension_space (insn_decode_record *arm_record) > +{ > + insn_decode_record *arm_insn_r =3D arm_record; > + struct gdbarch_tdep *tdep =3D gdbarch_tdep (arm_insn_r->gdbarch); > + struct regcache *reg_cache =3D arm_insn_r->regcache; > +=20=20=20=20 > + uint32_t reg_src1 =3D 0, reg_src2 =3D 0; > + uint32_t opcode1 =3D 0, opcode2 =3D 0; > + > + opcode1 =3D ARM_PARSE_INSN (arm_insn_r->arm_insn,26,3); > + if ((3 =3D=3D opcode1) && ARM_BIT_SET(arm_insn_r->arm_insn,5)) > + { > + /* undefined instruction on ARM V5; need to handle if later versio= ns > + define it. */ > + } > +=20=20 > + opcode2 =3D ARM_PARSE_INSN (arm_insn_r->arm_insn,5,4); > +=20=20 > + if ((!opcode1) && (9 =3D=3D opcode2)) > + { > + /* handle arithmetic insn extension space. */ > + } > + > + opcode1 =3D ARM_PARSE_INSN (arm_insn_r->arm_insn,27,2); ^ ^ You need an extra space after each comma. > + opcode2 =3D ARM_PARSE_INSN (arm_insn_r->arm_insn,24,2); > + > + if ((!opcode1) && (2 =3D=3D opcode2) && !ARM_BIT_SET(arm_insn_r->arm_i= nsn,21)) > + { > + /* handle control insn extension space. */ > + } > + > + opcode1 =3D ARM_PARSE_INSN (arm_insn_r->arm_insn,26,3); > + if ((!opcode1) && (ARM_BIT_SET(arm_insn_r->arm_insn,8)) \ > + && (ARM_BIT_SET(arm_insn_r->arm_insn,5))) > + { > + /* handle load/store insn extension space. */ > + } > + > + opcode1 =3D ARM_PARSE_INSN (arm_insn_r->arm_insn,24,5); > + if ((24 =3D=3D opcode1) && ARM_BIT_SET(arm_insn_r->arm_insn,22)) > + { > + /* handle coprocessor insn extension space. */ > + } > + > + /* to be done for ARMv5 and later; as of now we return -1. */ > + return -1; > +} > + > + > +/* Parse the current instruction and record the values of the registers = and > + memory that will be changed in current instruction to "record_arch_li= st". > + Return -1 if something is wrong.. */ > + > +int=20 > +arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache, > + CORE_ADDR insn_addr) > +{ > + > + enum bfd_endian byte_order =3D gdbarch_byte_order (gdbarch);=20=20 > + struct gdbarch_tdep *tdep =3D gdbarch_tdep (gdbarch); > + uint32_t no_of_rec=3D0; > + uint32_t ret=3D0; > + > + union > + { > + uint32_t s_word; > + gdb_byte buf[4]; > + } u_buf; > + > + insn_decode_record arm_record; > + memset (&u_buf, 0, sizeof(u_buf)); > + > + memset (&arm_record, 0, sizeof (insn_decode_record)); > + arm_record.regcache =3D regcache; > + arm_record.this_addr =3D insn_addr; > + arm_record.gdbarch =3D gdbarch; > + > + > + if (record_debug > 1) > + { > + fprintf_unfiltered (gdb_stdlog, "Process record: arm_process_recor= d " > + "addr =3D %s\n", > + paddress (gdbarch, arm_record.this_addr)); > + } > + > + /* check the insn, whether it is thumb or arm one. */ > + GET_REG_VAL (arm_record.regcache, ARM_PS_REGNUM, &u_buf.buf[0]); > + arm_record.cond =3D ARM_PARSE_INSN (arm_record.arm_insn,29,4);=20 > +=20=20 > + if (!IS_IT_ARM_INSN (u_buf.s_word)) Please reference to `arm_frame_is_thumb' or `displaced_in_arm_mode' to see how to check ARM mode or Thumb mode. > + { > + /* we are decoding arm insn. */ > + ret =3D decode_insn (&arm_record, ARM_INSN_SIZE_BYTES);=20=20=20= =20=20=20 > + } > + else > + { > + /* we are decoding thumb insn. */ > + ret =3D decode_insn (&arm_record, THUMB_INSN_SIZE_BYTES);=20=20=20= =20 On some ARM arch, there are 32-bit Thumb instructions, called Thumb-2. Do you plan to support Thumb-2 insn? > + } > + > + /* record registers. */ > + ARM_RECORD_ARCH_LIST_ADD_REG(ARM_PC_REGNUM); > + if (arm_record.arm_regs) > + { > + for (no_of_rec=3D1;no_of_rec<=3Darm_record.arm_regs[0];no_of_rec++) > + { > + if (ARM_RECORD_ARCH_LIST_ADD_REG (arm_record.arm_regs[no_of_re= c])) > + ret =3D -1; > + } > + }=20=20 > + /* record memories. */ > + if (arm_record.arm_mems) > + { > + for (no_of_rec=3D1;no_of_rec<=3Darm_record.arm_mems[0].len;no_of_r= ec++) > + { > + if (record_arch_list_add_mem \ > + ((CORE_ADDR)arm_record.arm_mems[no_of_rec].addr, > + arm_record.arm_mems[no_of_rec].len)) > + ret =3D -1; > + } > + } > + > + if (record_arch_list_add_end ()) > + ret =3D -1; > + > + if (arm_record.arm_regs) > + xfree (arm_record.arm_regs); > + if (arm_record.arm_mems) > + xfree (arm_record.arm_mems); > +=20=20 > + return ret;=20 > +} --=20 Yao (=E9=BD=90=E5=B0=A7)