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Date: Wed, 06 Jul 2005 23:16:00 -0000
From: Khem Raj <kraj@mvista.com>
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To: "'gdb@sources.redhat.com'" <gdb@sources.redhat.com>
Subject: [PATCH] arm: GDB disassembles ARM VFP 'fadds' instruction wrongly.
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Hello,

Like binutils, the following patch fixes the opcode disassembly for 
'fadds' ARM VFP instruction.
currently

fadds   s14, s14, s15

will be disassembled as

fadds   s14, s14, s14  by  gdb.

Is it ok ?

Thanks

-Khem

Changelog Entry:

2005-07-06  Khem Raj  <kraj@mvista.com>

       * arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction 
disassembly pattern.

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? diff
Index: arm-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/arm-dis.c,v
retrieving revision 1.48
diff -u -p -r1.48 arm-dis.c
--- arm-dis.c	8 Jun 2005 17:27:40 -0000	1.48
+++ arm-dis.c	6 Jul 2005 23:12:22 -0000
@@ -460,7 +460,7 @@ static const struct opcode32 arm_opcodes
   {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fff0ff0, "fabsd%c\t%1z, %0z"},
   {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%1y, %0y"},
   {FPU_VFP_EXT_V1, 0x0e300b00, 0x0ff00ff0, "faddd%c\t%1z, %2z, %0z"},
-  {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%1y, %2y, %1y"},
+  {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%1y, %2y, %0y"},
   {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fff0f70, "fcmp%7'ed%c\t%1z, %0z"},
   {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%1y, %0y"},
   {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fff0f70, "fcmp%7'ezd%c\t%1z"},

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