From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 2376 invoked by alias); 10 May 2002 14:03:05 -0000 Mailing-List: contact gdb-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sources.redhat.com Received: (qmail 2362 invoked from network); 10 May 2002 14:03:04 -0000 Received: from unknown (HELO beta.dmz-eu.st.com) (164.129.1.35) by sources.redhat.com with SMTP; 10 May 2002 14:03:04 -0000 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with SMTP id 645854E36; Fri, 10 May 2002 14:03:03 +0000 (GMT) Received: by zeta.dmz-eu.st.com (STMicroelectronics, from userid 0) id 50C5562BB; Fri, 10 May 2002 14:03:03 +0000 (GMT) Received: from thistle.bri.st.com (localhost [127.0.0.1]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7D4681845; Fri, 10 May 2002 14:03:02 +0000 (GMT) Received: from [164.129.8.14] (helo=masterwort) by thistle.bristol.st.com with esmtp (Exim 3.03 #5) id 176Az6-0005VE-00; Fri, 10 May 2002 15:03:00 +0100 Received: from [164.129.14.84] (helo=st.com) by masterwort with asmtp (Exim 3.22 #1) id 176Az6-0002Ku-00; Fri, 10 May 2002 15:03:00 +0100 Message-ID: <3CDBD33A.60D5768@st.com> Date: Fri, 10 May 2002 07:03:00 -0000 From: Joern Rennecke Reply-To: joern.rennecke@superh.com Organization: SuperH UK Ltd. X-Accept-Language: en MIME-Version: 1.0 To: ac131313@cygnus.com Cc: ezannoni@redhat.com, binutils@sources.redhat.com, gdb@sources.redhat.com, bje@redhat.com Subject: Re: SH simulator register numbers: include/gdb/sim-sh.h References: <3CCED903.294513BE@st.com> <15568.36275.110744.510692@localhost.redhat.com> <3CD12BF8.7E1650C1@st.com> <3CD7EB51.7816DD1@st.com> <3CD803BC.5060900@cygnus.com> <3CD823D1.FC1E3717@st.com> <3CD85192.7020100@cygnus.com> <3CDAEDA4.3DE4A2D5@st.com> <15578.63785.429521.553723@localhost.redhat.com> <3CDB0B49.3040700@cygnus.com> Content-Type: multipart/mixed; boundary="------------766A4160C38075DF2C38FC84" X-SW-Source: 2002-05/txt/msg00101.txt.bz2 This is a multi-part message in MIME format. --------------766A4160C38075DF2C38FC84 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Content-length: 532 > BTW, GDB has started moving the include/sim-*.h files into > include/gdb/sim-*.h, but otherwise, yes. Right, so the simulator interface would go into include/gdb/sim-sh.h . Fri May 10 14:58:33 2002 J"orn Rennecke * sim-sh.h: New file, from include/sim-sh64.h. Added SH1-SH4 / SH-DSP register numbers, moved SH5 register numbers, added full set of control registers. -- -------------------------- SuperH 2430 Aztec West / Almondsbury / BRISTOL / BS32 4AQ T:+44 1454 462330 --------------766A4160C38075DF2C38FC84 Content-Type: text/plain; charset=us-ascii; name="sim-sh.h" Content-Transfer-Encoding: 7bit Content-Disposition: inline; filename="sim-sh.h" Content-length: 4826 /* This file defines the interface between the sh64 simulator and gdb. Copyright (C) 2000, 2002 Free Software Foundation, Inc. This file is part of GDB. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #if !defined (SIM_SH_H) #define SIM_SH_H #ifdef __cplusplus extern "C" { // } #endif /* The simulator makes use of the following register information. */ enum { SIM_SH_R0_REGNUM = 0, SIM_SH_R1_REGNUM, SIM_SH_R2_REGNUM, SIM_SH_R3_REGNUM, SIM_SH_R4_REGNUM, SIM_SH_R5_REGNUM, SIM_SH_R6_REGNUM, SIM_SH_R7_REGNUM, SIM_SH_R8_REGNUM, SIM_SH_R9_REGNUM, SIM_SH_R10_REGNUM, SIM_SH_R11_REGNUM, SIM_SH_R12_REGNUM, SIM_SH_R13_REGNUM, SIM_SH_R14_REGNUM, SIM_SH_R15_REGNUM, SIM_SH_PC_REGNUM, SIM_SH_PR_REGNUM, SIM_SH_GBR_REGNUM, SIM_SH_VBR_REGNUM, SIM_SH_MACH_REGNUM, SIM_SH_MACL_REGNUM, SIM_SH_SR_REGNUM, SIM_SH_FPUL_REGNUM, SIM_SH_FPSCR_REGNUM, SIM_SH_FR0_REGNUM = 25, /* sh3e / sh4 */ /* sh[3]-dsp */ SIM_SH_DSR_REGNUM = 24, SIM_SH_A0G_REGNUM, SIM_SH_A0_REGNUM, SIM_SH_A1G_REGNUM, SIM_SH_A1_REGNUM, SIM_SH_M0_REGNUM, SIM_SH_M1_REGNUM, SIM_SH_X0_REGNUM, SIM_SH_X1_REGNUM, SIM_SH_Y0_REGNUM, SIM_SH_Y1_REGNUM, SIM_SH_MOD_REGNUM = 40, SIM_SH_SSR_REGNUM = 41, SIM_SH_SPC_REGNUM, /* sh3{,e,-dsp}, sh4 */ SIM_SH_RS_REGNUM = 43, SIM_SH_RE_REGNUM, /* sh[3]-dsp */ SIM_SH_R0_BANK0_REGNUM = 43, SIM_SH_R7_BANK0_REGNUM = 50, /* sh3[e] / sh4 */ SIM_SH_R0_BANK1_REGNUM = 51, SIM_SH_R7_BANK1_REGNUM = 58, /* sh3[e] / sh4 */ SIM_SH_R0_BANK_REGNUM = 51, SIM_SH_R7_BANK_REGNUM = 58, /* sh[3]-dsp */ SIM_SH_XF0_REGNUM = 59, SIM_SH_SGR_REGNUM = 75, SIM_SH_DBR_REGNUM = 76, SIM_SH4_NUM_REGS, /* 77..127: room for expansion. */ SIM_SH64_R0_REGNUM = 128, SIM_SH64_SP_REGNUM = SIM_SH64_R0_REGNUM+15, SIM_SH64_PC_REGNUM = SIM_SH64_R0_REGNUM+64, /* 64 64-bit control registers */ SIM_SH64_CR0_REGNUM = SIM_SH64_R0_REGNUM+65, SIM_SH64_SR_REGNUM = SIM_SH64_CR0_REGNUM, /* Status reg */ SIM_SH64_SSR_REGNUM = SIM_SH64_CR0_REGNUM+1, /* Saved status reg */ SIM_SH64_PSSR_REGNUM = SIM_SH64_CR0_REGNUM+2, /* Panic-saved status reg*/ SIM_SH64_INTEVT_REGNUM=SIM_SH64_CR0_REGNUM+4, /* Interrupt event reg */ SIM_SH64_EXPEVT_REGNUM=SIM_SH64_CR0_REGNUM+5, /* Exception event reg */ SIM_SH64_PEXPEVT_REGNUM= SIM_SH64_CR0_REGNUM+6,/* Panic-saved Exception event reg */ SIM_SH64_TRA_REGNUM = SIM_SH64_CR0_REGNUM+7, /* TRAP exception reg */ SIM_SH64_SPC_REGNUM = SIM_SH64_CR0_REGNUM+8, /* Saved program counter */ SIM_SH64_PSPC_REGNUM = SIM_SH64_CR0_REGNUM+9, /* Panic-saved program counter */ SIM_SH64_RESVEC_REGNUM=SIM_SH64_CR0_REGNUM+10, /* Reset vector */ SIM_SH64_VBR_REGNUM = SIM_SH64_CR0_REGNUM+11, /* Vector base register */ SIM_SH64_TEA_REGNUM = SIM_SH64_CR0_REGNUM+13, /* Faulting effective address register */ SIM_SH64_DCR_REGNUM = SIM_SH64_CR0_REGNUM+16, /* Debug control reg */ SIM_SH64_KCR0_REGNUM = SIM_SH64_CR0_REGNUM+17, /* Kernel register 0 */ SIM_SH64_KCR1_REGNUM = SIM_SH64_CR0_REGNUM+18, /* Kernel register 1 */ SIM_SH64_CTC_REGNUM = SIM_SH64_CR0_REGNUM+62, /* Clock tick counter */ SIM_SH64_USR_REGNUM = SIM_SH64_CR0_REGNUM+63, /* User-accessible status register */ SIM_SH64_CR63_REGNUM = SIM_SH64_R0_REGNUM+128, SIM_SH64_TR0_REGNUM = SIM_SH64_R0_REGNUM+129, SIM_SH64_FPSCR_REGNUM= SIM_SH64_R0_REGNUM+137, SIM_SH64_FR0_REGNUM = SIM_SH64_R0_REGNUM+138 }; enum { SIM_SH64_NUM_REGS = 202, /* total number of architectural registers */ SIM_SH64_NR_R_REGS = 64, /* number of general registers */ SIM_SH64_NR_TR_REGS = 8, /* number of target registers */ SIM_SH64_NR_FP_REGS = 64, /* number of floating point registers */ SIM_SH64_FPSCR_OFFSET = (SIM_SH64_FPSCR_REGNUM - SIM_SH64_R0_REGNUM) * 8, SIM_SH64_FR0_OFFSET = (SIM_SH64_FPSCR_REGNUM - SIM_SH64_R0_REGNUM) * 8 + 4 }; enum { SIM_SH4_REG_BYTES = SIM_SH4_NUM_REGS * 4, SIM_SH64_REG_BYTES = SIM_SH64_NUM_REGS * 8 - (SIM_SH64_NR_FP_REGS + 1) * 4 }; #ifdef __cplusplus } #endif #endif --------------766A4160C38075DF2C38FC84--