From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15281 invoked by alias); 21 Jan 2009 11:09:05 -0000 Received: (qmail 15266 invoked by uid 22791); 21 Jan 2009 11:09:04 -0000 X-SWARE-Spam-Status: No, hits=-2.1 required=5.0 tests=AWL,BAYES_00,J_CHICKENPOX_35 X-Spam-Check-By: sourceware.org Received: from rock.gnat.com (HELO rock.gnat.com) (205.232.38.15) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 21 Jan 2009 11:08:57 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by filtered-rock.gnat.com (Postfix) with ESMTP id 9B9392A95EB; Wed, 21 Jan 2009 06:08:55 -0500 (EST) Received: from rock.gnat.com ([127.0.0.1]) by localhost (rock.gnat.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 0nuxNscCEE+P; Wed, 21 Jan 2009 06:08:55 -0500 (EST) Received: from joel.gnat.com (localhost.localdomain [127.0.0.1]) by rock.gnat.com (Postfix) with ESMTP id C6E732A95EA; Wed, 21 Jan 2009 06:08:54 -0500 (EST) Received: by joel.gnat.com (Postfix, from userid 1000) id EB828E7ACD; Wed, 21 Jan 2009 15:08:47 +0400 (RET) Date: Wed, 21 Jan 2009 11:09:00 -0000 From: Joel Brobecker To: gcc@gcc.gnu.org, gdb@sourceware.org Subject: DWARF register numbering discrepancy on SPARC between GCC and GDB Message-ID: <20090121110847.GU5709@adacore.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.4.2.2i Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org X-SW-Source: 2009-01/txt/msg00137.txt.bz2 Hello, Eric and I discovered a discrepancy in the DWARF register numbering on SPARC for floating point registers. The problem is more visible on SPARC 64-bit because they are used for parameter passing, whether i0 is used on 32-bit SPARC. Consider for instance the following code: volatile register float r asm("f0"); int foo(float f) { r = f; } At -O0 -g: st %i0, [%fp+68] ld [%fp+68], %f0 .byte 0x5 ! uleb128 0x5; (DIE (0xd2) DW_TAG_variable) .ascii "r\0" ! DW_AT_name .byte 0x1 ! DW_AT_decl_file (t.c) .byte 0x1 ! DW_AT_decl_line .uaword 0xdf ! DW_AT_type .byte 0x1 ! DW_AT_external .byte 0x2 ! DW_AT_location .byte 0x90 ! DW_OP_regx !!-> .byte 0x28 ! uleb128 0x28 .byte 0x6 ! uleb128 0x6; (DIE (0xdf) DW_TAG_volatile_type) .uaword 0xc9 ! DW_AT_type As you can see, GCC tells us that variable "r" is in register 0x28=40. The problem is that GCC thinks that register 40 is f0, whereas GDB thinks that register 32 is f0. More generally, GCC thinks that registers f0-f31 should be numbered 40-71: /* Define how the SPARC registers should be numbered for Dwarf output. The numbering provided here should be compatible with the native svr4 SDB debugger in the SPARC/svr4 reference port. The numbering is as follows: Assembly name gcc internal regno Dwarf regno ---------------------------------------------------------- g0-g7 0-7 0-7 o0-o7 8-15 8-15 l0-l7 16-23 16-23 i0-i7 24-31 24-31 f0-f31 32-63 40-71 According to Eric, this has been like that for the past since 1992. However, when I tried to find some kind of official document to confirm this numbering, I only found: http://wikis.sun.com/display/SunStudio/Dwarf+Register+Numbering This is a wiki page, so I'm not sure how much we can trust the contents. However, it does contradict the numbers above: Apparently DBX expects f0-f31 to be numbered 32-63, not 40-71. If that information is correct, perhaps Sun changed it since the first implementation in SDB? Does anyone have maybe a more affirmative document? The decision we need to make is to decide whether to change GDB to match GCC or to change GCC. Changing GDB shouldn't be very hard, but I think we should choose the same numbering scheme as DBX. Opinions? Thank you! -- Joel