Re: How to avoid stepping inside libpthread

Atsushi Nemoto
2007-07-12T06:31:04Z

On Thu, 12 Jul 2007 11:15:40 +0900 (JST), Atsushi Nemoto <anemo@mba.ocn.ne.jp> wrote:
> > See deal_with_atomic_sequence in rs6000-tdep.c, which tries to solve the
> > same issue.
>
> Thank you. I'll try to implement the feature for mips.

Thanks, it worked. Here is a patch against gdb-6.6.

I'll port this patch to current gdb, but while it seems current gdb
cannot find libpthread symbol, another test code (or fixing gdb) would
be needed first ...

--- gdb-6.6.org/gdb/mips-tdep.c 2006-08-09 06:32:37.000000000 +0900
+++ gdb-6.6/gdb/mips-tdep.c 2007-07-12 14:11:46.000000000 +0900
@@ -2177,6 +2177,86 @@ mips_addr_bits_remove (CORE_ADDR addr)
return addr;
}

+/* Instruction masks used during single-stepping of atomic sequences. */
+#define LLSC_MASK 0xfc000000
+#define LL_INSTRUCTION 0xc0000000
+#define LLD_INSTRUCTION 0xd0000000
+#define SC_INSTRUCTION 0xe0000000
+#define SCD_INSTRUCTION 0xf0000000
+
+/* Checks for an atomic sequence of instructions beginning with a LL/LLD
+ instruction and ending with a SC/SCD instruction. If such a sequence
+ is found, attempt to step through it. A breakpoint is placed at the end of
+ the sequence. */
+
+static int
+deal_with_atomic_sequence (CORE_ADDR pc)
+{
+ CORE_ADDR breaks[2] = {-1, -1};
+ CORE_ADDR loc = pc;
+ CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
+ int insn;
+ int insn_count;
+ int index;
+ int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
+ const int atomic_sequence_length = 16; /* Instruction sequence length. */
+
+ if (pc & 0x01)
+ return 0;
+
+ insn = mips_fetch_instruction (loc);
+ /* Assume all atomic sequences start with a ll/lld instruction. */
+ if ((insn & LLSC_MASK) != LL_INSTRUCTION
+ && (insn & LLSC_MASK) != LLD_INSTRUCTION)
+ return 0;
+
+ /* Assume that no atomic sequence is longer than "atomic_sequence_length"
+ instructions. */
+ for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
+ {
+ loc += MIPS_INSN32_SIZE;
+ insn = mips_fetch_instruction (loc);
+
+ /* Assume that there is at most one branch in the atomic
+ sequence. If a branch is found, put a breakpoint in its
+ destination address. */
+ branch_bp = mips_next_pc (loc);
+ if (branch_bp != loc + MIPS_INSN32_SIZE)
+ {
+ if (last_breakpoint >= 1)
+ return 0; /* More than one branch found, fallback to the
+ standard single-step code. */
+ breaks[1] = branch_bp;
+ last_breakpoint++;
+ }
+
+ if ((insn & LLSC_MASK) == SC_INSTRUCTION
+ || (insn & LLSC_MASK) == SCD_INSTRUCTION)
+ break;
+ }
+
+ /* Assume that the atomic sequence ends with a sc/scd instruction. */
+ if ((insn & LLSC_MASK) != SC_INSTRUCTION
+ && (insn & LLSC_MASK) != SCD_INSTRUCTION)
+ return 0;
+
+ loc += MIPS_INSN32_SIZE;
+
+ /* Insert a breakpoint right after the end of the atomic sequence. */
+ breaks[0] = loc;
+
+ /* Check for duplicated breakpoints. Check also for a breakpoint
+ placed (branch instruction's destination) in the atomic sequence */
+ if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
+ last_breakpoint = 0;
+
+ /* Effectively inserts the breakpoints. */
+ for (index = 0; index <= last_breakpoint; index++)
+ insert_single_step_breakpoint (breaks[index]);
+
+ return 1;
+}
+
/* mips_software_single_step() is called just before we want to resume
the inferior, if we want to single-step it but there is no hardware
or kernel single-step support (MIPS on GNU/Linux for example). We find
@@ -2193,6 +2273,9 @@ mips_software_single_step (enum target_s
if (insert_breakpoints_p)
{
pc = read_register (mips_regnum (current_gdbarch)->pc);
+ if (deal_with_atomic_sequence (pc))
+ return;
+
next_pc = mips_next_pc (pc);

insert_single_step_breakpoint (next_pc);