Re: Can this be happening?

Balazs Scheidler
2007-07-05T19:26:37Z

On Tue, 2007-07-03 at 17:57 -0400, Daniel Jacobowitz wrote:
> On Tue, Jul 03, 2007 at 02:38:51PM -0700, Jim Blandy wrote:
> > I don't know why the upper bits would be set. GDB may be
> > misinterpreting the information in the core file.
>
> The kernel dumps it as 32-bit too. It's not clear what those bits are
> for, but I bet they're really in your core dump and you should ask the
> kernel developers.
>
> Moves from the segment registers may leave implementation defined data
> in the upper half register - but that's only for fairly old Intel
> processors.
>

IIRC the processor-defined TSS (Task State Segment) uses 32 bit values
for segment registers, although as I know TSS is not used anymore by
recent kernels.

--
Bazsi