Re: hardware support for gdb?

[Peter Barada <peter@the-baradas.com>]

>What I understood from this paragraph is that, if a target processor provide
>"trace bit" kind of functionality, gdb developer's life is easier otherwise
>he has to do some more work(disassembling of instruction). Am I right? Could
>you please explain a little about "trace bit" or similar functionality? Is
>it the breakpoint instruction, you mentioned about?

For more info on a 'trace' bit type architecture, look up any 68000 or
ColdFire processor manual.  In a nutshell, in an exception, if you patch the
status register value to or in the trace bit, then when the return
from exception is taken, the processor will execute *one* instruction
and then take an exception.  This allows you to step the processor one
instruction at a time without affecting its execution.

If the processor does not have this capability, then gdb inserts an
illegal instruction following the instruction it wants to step.  The
instruction needs to be decoded so if there is a possible branch(or
return or jump-to-subroutine), GDB can place another illegal
instruction at the target of the branch.   This can take quite a while
if GDB is comminication with the target via a slow serial line...

-- 
Peter Barada
peter@the-baradas.com