From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20785 invoked by alias); 4 Sep 2003 00:17:50 -0000 Mailing-List: contact gdb-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sources.redhat.com Received: (qmail 20778 invoked from network); 4 Sep 2003 00:17:49 -0000 Received: from unknown (HELO animal.blarg.net) (206.124.128.1) by sources.redhat.com with SMTP; 4 Sep 2003 00:17:49 -0000 Received: by animal.blarg.net (Postfix, from userid 3118) id EE9F66F5BA; Wed, 3 Sep 2003 17:17:48 -0700 (PDT) Date: Thu, 04 Sep 2003 00:17:00 -0000 From: Ben Johnson To: Andrew Cagney Cc: gdb@sources.redhat.com Subject: Re: how are debug registers supposed to work? Message-ID: <20030903171748.A3111@blarg.net> References: <20030828174129.B9184@blarg.net> <3F567176.1000100@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.2.5.1i In-Reply-To: <3F567176.1000100@redhat.com>; from ac131313@redhat.com on Wed, Sep 03, 2003 at 06:55:50PM -0400 X-SW-Source: 2003-09/txt/msg00049.txt.bz2 Thanks for the response. Everything on this box is carefully (as possible) controlled. I have removed all reference to the debug registers throughout the kernel. (I don't know if they can be accessed directly from user space, but I would guess not.) I've turned on the 'GD' bit in %db7. That causes a debug exception (int1) to be thrown when any of the debug registers are accessed or written to. I believe they're not be fooled with because, unless I purposefully read or write to the debug regs now, I never get a debug exception. I've tried setting both code and data break/watchpoints, and none of them seem to work at all. I know the interrupt handler is setup correctly because I do get the interrupt when the GD bit is set and I try to read %db7. I've found no other way to make these register do anything though. I've given up. I think they just don't work. but, how could they not work? There *must* be something I'm not understanding. I gave up leaving anything to chance and started putting code like this in the (2.0 Kernel) schedule() function: if( first_time ) { static unsigned long testvar = 0; unsigned long db7; first_time = 0; /* maybe flush and disable the cache here. doesn't matter. */ asm ("movl %0, %%db0\n" " movl %1, %%db7\n" : /* no output */ :"a"(&testvar), /* put &testvar in db0 */ "b"(0x000f2202) /* watch 4 bytes for reads or writes * at &testvar globally and set GD */ ); testvar = 0xffffffff; /* change all the bits */ /* should get a debug exception here */ printk(KERN_DEBUG "%s: any luck?\n", __FUNCTION__); asm ("movl %%db7, %0\n" /* this movl triggers a debug exception. */ :"=a"(db7) ); } What am I not getting? I think there must be another bit I need to set or the data I'm using is not properly aligned (in some way I don't understand) or maybe this register has to be enabled by the bios? who knows. - Ben On Wed, Sep 03, 2003 at 06:55:50PM -0400, Andrew Cagney wrote: > > Just a thought, you're not fighting a user space process playing with > those registers? > > The other is to look at GDB using hardware debug registers on a user > process. > > Andrew > >