From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 763 invoked by alias); 16 May 2002 13:59:52 -0000 Mailing-List: contact gdb-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sources.redhat.com Received: (qmail 723 invoked from network); 16 May 2002 13:59:48 -0000 Received: from unknown (HELO fw-cam.cambridge.arm.com) (193.131.176.3) by sources.redhat.com with SMTP; 16 May 2002 13:59:48 -0000 Received: by fw-cam.cambridge.arm.com; id OAA20395; Thu, 16 May 2002 14:59:46 +0100 (BST) Received: from unknown(172.16.1.2) by fw-cam.cambridge.arm.com via smap (V5.5) id xma019832; Thu, 16 May 02 14:59:03 +0100 Received: from cam-mail2.cambridge.arm.com (cam-mail2.cambridge.arm.com [172.16.1.91]) by cam-admin0.cambridge.arm.com (8.9.3/8.9.3) with ESMTP id OAA24891; Thu, 16 May 2002 14:59:02 +0100 (BST) Received: from sun18.cambridge.arm.com (sun18.cambridge.arm.com [172.16.2.18]) by cam-mail2.cambridge.arm.com (8.9.3/8.9.3) with ESMTP id OAA28147; Thu, 16 May 2002 14:59:00 +0100 (BST) Message-Id: <200205161359.OAA28147@cam-mail2.cambridge.arm.com> To: Andrew Cagney cc: Richard.Earnshaw@arm.com, Eli Zaretskii , gdb@sources.redhat.com Reply-To: Richard.Earnshaw@arm.com Organization: ARM Ltd. X-Telephone: +44 1223 400569 (direct+voicemail), +44 1223 400400 (switchbd) X-Fax: +44 1223 400410 X-Address: ARM Ltd., 110 Fulbourn Road, Cherry Hinton, Cambridge CB1 9NJ. X-Url: http://www.arm.com/ Subject: Re: Multi-arch and user-control of architecture flags In-reply-to: Your message of "Thu, 16 May 2002 09:50:02 EDT." <3CE3B90A.1000904@cygnus.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Thu, 16 May 2002 06:59:00 -0000 From: Richard Earnshaw X-SW-Source: 2002-05/txt/msg00189.txt.bz2 > > /* Add root prefix command for all "set mips"/"show mips" commands */ > > add_prefix_cmd ("mips", no_class, set_mips_command, > > "Various MIPS specific commands.", > > &setmipscmdlist, "set mips ", 0, &setlist); > > > > add_prefix_cmd ("mips", no_class, show_mips_command, > > "Various MIPS specific commands.", > > &showmipscmdlist, "show mips ", 0, &showlist); > > > > Just a PS on this. The command set ``set mips fpu ...'' et.al. isn't > perfect - it sets a global for all mips which is probably sufficient for > what people want. > > Eventually a per thread command may be needed. So that a target > containing an 8086 and x86-64 can have, separatly, their disassembly > mode. Something like: > > thread 5 set i386 disassembler x86-64 > > (just ignore the syntax though). However, not our problem :-) > Yeah! I was thinking of a similar sort of requirement if a user has two physical CPUs in the design, then you would need to be able to configure each instance. However, we would need to be able to have multiple instances of the gdbarch current for that to work... R.