From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 11244 invoked by alias); 10 Feb 2006 12:05:41 -0000 Received: (qmail 11235 invoked by uid 22791); 10 Feb 2006 12:05:41 -0000 X-Spam-Check-By: sourceware.org Received: from ac-202-238-16-ind.acmet.com (HELO alice.acmet.com) (61.16.238.202) by sourceware.org (qpsmtpd/0.31) with ESMTP; Fri, 10 Feb 2006 12:05:39 +0000 Received: from [192.168.0.217] (localhost [127.0.0.1] (may be forged)) by alice.acmet.com (8.11.6/8.11.6) with ESMTP id k1AC6CJ24836; Fri, 10 Feb 2006 17:36:12 +0530 Subject: Re: Resume from Breakpoint - Next Instruction Address or Target Address? From: Rishi Dixit Reply-To: dixit_rishi@acmet.com To: Daniel Jacobowitz Cc: Mailing List In-Reply-To: <20060206234711.GA523@nevyn.them.org> References: <1138623528.3621.173.camel@rishidixit> <20060206234711.GA523@nevyn.them.org> Content-Type: text/plain Message-Id: <1139573166.3619.0.camel@rishidixit> Mime-Version: 1.0 Date: Fri, 10 Feb 2006 12:05:00 -0000 Content-Transfer-Encoding: 7bit X-IsSubscribed: yes Mailing-List: contact gdb-help@sourceware.org; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-owner@sourceware.org X-SW-Source: 2006-02/txt/msg00077.txt.bz2 On Tue, 2006-02-07 at 05:17, Daniel Jacobowitz wrote: > On Mon, Jan 30, 2006 at 05:48:48PM +0530, Rishi Dixit wrote: > > Hi, > > > > > > I am studying about breakpoint functionality in GDB. My study is local > > to the MIPS Simulator. While studying the GDB source, I was referring > > the handling of BREAK instruction. > > > > This handling checks for the presence of BREAK instruction in a delay > > slot and alters the Program Counter. However, this information is > > overwritten when the CPU registers are saved before triggering a > > Breakpoint exception. > > > > I suspected this would lead to a loss of information regarding the > > target address of jump/branch instruction. To confirm this, I made a > > test case and checked the GDB behavior. > > I don't know - you'd have to ask someone more familiar with the > architecture and the simulator - but I think this is a bug in either > the simulator or GDB; the architecture does provide enough information > to handle this case. See the documentation of the BD bit in the Cause > register. I tried some modifications based on this information in the documentation. These were done before the handling of the Breakpoint Exception, which is raised whenever a Breakpoint is hit. However, if the value of Program Counter is altered then the handling of breakpoints in GDB is disturbed. Another angle is that this can be checked for when the simulator is resuming after the exception has been serviced. When this is being done, the program counter can be altered based on the information of the BD bit in Cause register. > > My assumption is that since the breakpoint is hit after the jump/branch > > instruction has been executed, the resume should be from the target > > address. > > No, generally we want to resume where we were, not where we're going > to. The resume should be back on the jump. I have no idea if GDB > implements that. Thanks for clearing my doubt. The resume should be from the preceding branch/jump instruction. After this instruction is processed, the control jumps to the target address.